一款多核处理器FPGA验证平台的设计与实现

发布时间：2018-05-03 03:13

本文选题：FPGA原型验证 + FPGA分片　；参考：《计算机研究与发展》2014年06期

【摘要】：高性能处理器设计日趋复杂,为了缩短验证周期,降低研制风险通常需要在流片之前进行基于现场可编程门阵列(field programmable gate-array,FPGA)原型验证平台的软硬件协同验证.随着处理器多核化的发展,FPGA原型验证平台的实现变得越来越具有挑战性.介绍了一款高性能多核微处理器FPGA验证平台的设计与实现方法,详细阐述了该FPGA验证平台采用的母板/子板总体架构、分片策略、时分复用实现技术及I/O接口实现方法.该平台具有良好的可扩展性,能够方便灵活地实现目标芯片在各种规模和配置下的FPGA验证,用于在流片前对目标芯片进行功能正确性验证和性能评估.经过该FPGA平台验证的目标芯片,首次流片返回的芯片能成功运行操作系统和各种应用程序,实现了一次流片成功的目标.最后对该FPGA验证平台的应用前景进行了分析总结.
[Abstract]:The design of high performance processors is becoming more and more complex. In order to shorten the verification period and reduce the development risk, the hardware and software co-verification based on the field programmable gate-array FPGA prototype verification platform is usually needed before the flow sheet. With the development of processor multicore, the implementation of FPGA prototype verification platform becomes more and more challenging. This paper introduces the design and implementation of a high performance multi-core microprocessor FPGA verification platform. The master board / sub-board architecture, slicing strategy, time division multiplexing (TDM) and I / O interface implementation of the FPGA verification platform are described in detail. The platform has good expansibility and can easily and flexibly implement the FPGA verification of the target chip under various scales and configurations. It can be used to verify the functional correctness and evaluate the performance of the target chip before streaming chip. The target chip verified by the FPGA platform, the chip returned for the first time can run the operating system and all kinds of applications successfully, and achieve the goal of a single stream chip successfully. Finally, the application prospect of the FPGA verification platform is analyzed and summarized.
【作者单位】：上海高性能集成电路设计中心;
【基金】：“核高基”国家科技重大专项基金项目(2009ZX01028-002-001)
【分类号】：TP332

【参考文献】