OTP存储器设计与实现技术研究

发布时间：2018-05-03 09:37

本文选题：OTP存储器 + 电荷泵　；参考：《电子科技大学》2012年硕士论文

【摘要】：OTP存储器的功能介于Mask ROM和EPROM之间,既给用户提供一定自由配置的空间又无需复杂的擦除机制,所以其电路结构简单且可靠性高,被广泛应用于密钥保存、嵌入式存储及空间军事应用。论文旨在设计实现一款功能正确性能良好的OTP存储器。论文参考了国内外OTP存储单元的设计方案,分析了存储单元的工作原理,对其结构进行了设计。由于编程后的特性难以在仿真上体现,存储单元在实际工艺线上进行了流片并完成了测试。以存储单元的实测结果为基础,讨论了存储器外围电路的构建方案。其中多维译码方式配合了存储阵列的排布并且缩短了延迟时间；编程电路采用高压复制型的电荷泵,在芯片内部有选择地产生编程高压,减小了高压信号对内部电路和存储阵列的影响；读取电路以位线充放电过程为基础,具有较短读取时间和较大的读取阈值；片选和输出使能模块为更高一级系统对存储器的调用提供了基础,能降低整体系统功耗,也和译码信号一起为编程和读取过程起到了控制作用。外围电路的逻辑功能使用Spectre仿真得到了验证。电路构建完成之后进行了存储器整体版图的设计并在0.18μm工艺上进行了流片。版图设计中考虑了各类可制造性设计问题以提高芯片制造良率,并在关键信号处设置了测试点以供芯片测试过程中错误的排查。使用Calibre验证了版图设计规则和连接关系,并解决了特殊器件的网表提取等细节问题。在此基础上提取了寄生参数并使用Finesim工具进行后仿真。流片后对芯片进行了实际测试。后仿真和实测结果都表明读写功能正确,电荷泵可以产生所需高压完成编程过程,读取模块可以针对阻值较高的存储单元进行,且具有较短的读取时间。论文在常规商用工艺基础上成功设计实现了一款64Kbit OTP存储器芯片,功能正确、性能良好,满足预期要求。
[Abstract]:The function of OTP memory lies between Mask ROM and EPROM, which not only provides users with free configuration space but also does not need complicated erasure mechanism, so its circuit structure is simple and reliable, so it is widely used in key preservation. Embedded storage and space military applications. The purpose of this paper is to design and implement a functional OTP memory with good performance. Referring to the design scheme of OTP storage cell at home and abroad, the working principle of memory cell is analyzed, and its structure is designed. Because the characteristics of the program are difficult to be realized in the simulation, the memory cell is carried out on the actual process line and the test is completed. Based on the measured results of the memory cell, the construction scheme of the memory peripheral circuit is discussed. The multidimensional decoding method is combined with the arrangement of the memory array and the delay time is shortened; the programming circuit uses a high-voltage replication-type charge pump to selectively generate the programming high voltage inside the chip. The influence of high voltage signal on internal circuit and memory array is reduced, the reading circuit is based on the charging and discharging process of bit line, and has a short reading time and a large reading threshold. The chip selection and output enable module provide the basis for the higher level system to call the memory, reduce the overall system power consumption, and together with the decoding signal, play a controlling role in the programming and reading process. The logic function of peripheral circuit is verified by Spectre simulation. After the circuit is constructed, the whole memory layout is designed and the wafer is made on 0.18 渭 m process. In the layout design, various kinds of manufacturability design problems are considered to improve the chip manufacturing yield, and the test points are set at the key signals for the error detection during the chip testing process. The rules of layout design and the connection relation are verified by Calibre, and the detailed problems such as nettable extraction of special devices are solved. On this basis, the parasitic parameters are extracted and then simulated by Finesim tool. The chip is tested after streaming. The post-simulation and measured results show that the reading and writing function is correct, the charge pump can generate the required high voltage to complete the programming process, the reading module can be carried out for the memory cell with higher resistance value, and the reading time is shorter. On the basis of conventional commercial technology, a 64Kbit OTP memory chip is successfully designed and implemented in this paper.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

【参考文献】