基于闪存阵列的高速数据存储技术研究

发布时间：2018-05-04 20:12

本文选题：闪速存储器 + 存储阵列　；参考：《中北大学》2012年硕士论文

【摘要】：课题针对单片NAND型闪速存储器存储容量较小和存储速度较慢的特点，通过构建闪存阵列的方式来增大存储容量、提高存储速度实现了大容量高速存储。利用位扩展技术完成了以单片NAND FLASH为基本存储单元的存储阵列的横向扩展，利用分时加载技术实现了纵向的扩展，构建了m×n的通用阵列。然后提出了对存储阵列中无效块的处理方法，根据阵列的行列m、n的取值不同分别提出了全相关、全独立、行相关、列相关四种管理机制。在进一步研究阵列的工作原理之后，为存储阵列设计了专用的DMA逻辑控制电路。最后，讨论了存储阵列的数据管理方法，在各个相关模块的存储阵列中建立系统信息区、状态标识区、文件信息区、参数配置区、数据存储区，这样能方便有效的存储和管理测试数据。在提出存储阵列的构建、存储阵列工作原理、无效块处理机制和数据管理方法之后，本文还通过动态参数测试系统的设计为例，介绍了存储阵列在测试系统中的应用。测试系统包括FPGA主控系统、模数转换模块、FLASH存储阵列、USB接口电路等。主控系统采用的是以FPGA为载体的SOPC系统，SOPC内部集成了Microblaze软核处理器及用户自行设计的IP核，用户IP是完成采集存储的核心电路；模数转换模块支持2、4、8、16四种可选通道的同步数据采集，在16通道同步采集的状态下，采样速率能达到400ksps；FLASH存储阵列系统采用1×4的阵列，，无效块处理机制采用行相关方式；USB接口电路主要作用是为处理器和上位机提供数据通道，方便测试系统接收来至上位机的各种操作命令，以及保证测试数据的顺利回传。最后通过测试实验验证了存储阵列的存储速度能达到16.6MB/s，也保证了测试系统的可靠性。
[Abstract]:In view of the small storage capacity and slow storage speed of single-chip NAND flash memory, a flash memory array is constructed to increase the storage capacity and achieve high speed storage. The horizontal expansion of memory array based on monolithic NAND FLASH is accomplished by bit expansion technique, and the longitudinal extension is realized by time-sharing loading technique, and a general m 脳 n array is constructed. Then, the processing method of invalid blocks in memory array is proposed. According to the different values of column and column MN of the array, four management mechanisms are proposed: full correlation, full independence, row correlation and column correlation. After further studying the working principle of the array, a special DMA logic control circuit is designed for the storage array. Finally, the data management method of the storage array is discussed. The system information area, the status identification area, the file information area, the parameter configuration area, the data storage area are established in the storage array of each related module. In this way, the test data can be stored and managed conveniently and effectively. After putting forward the construction of storage array, the working principle of storage array, the processing mechanism of invalid block and the method of data management, this paper also introduces the application of storage array in the test system through the design of dynamic parameter test system as an example. The test system includes FPGA main control system, A-D conversion module flash memory array and USB interface circuit. The main control system adopts the SOPC system based on FPGA, which integrates the Microblaze soft core processor and the IP core designed by the user. The user IP is the core circuit to complete the acquisition and storage. The analog-to-digital conversion module supports the synchronous data acquisition of 4 optional channels, and the sampling rate can reach 400 ksps / flash memory array system using 1 脳 4 array under the state of 16-channel synchronous acquisition. The main function of the invalid block processing mechanism is to provide the data channel for the processor and the host computer by using the row correlation mode and USB interface circuit, to facilitate the test system to receive all kinds of operation commands to the host computer, and to ensure the smooth return of the test data. Finally, the test results show that the storage speed of the memory array can reach 16.6 Mb / s, and the reliability of the test system is guaranteed.
【学位授予单位】：中北大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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