一种并行计算机互连网络中的地址转换Cache

发布时间：2018-05-05 23:03

本文选题：并行计算机 + 互连网络　；参考：《计算机研究与发展》2016年02期

【摘要】：当前在大规模并行计算机中,多数并行程序的用户习惯于使用虚拟地址进行编程.因此,虚拟地址与物理地址之间的转换效率直接影响了并行程序的执行性能,而cache能够有效地提高虚实地址转换的效率并降低延迟.提出了一种在大规模并行计算机互连网络中的地址转换cache.它采用了嵌入式DRAM(embedded dynamic random access memory,eDRAM)存储器,容纳更多的地址转换表项,从而提高命中率.并设计一种eDRAM刷新机制,隐藏了刷新操作,避免刷新导致的性能损失.ATC(address translation cache)中实现了诸如纠错码与旁路机制等多种可靠性设计.在32个计算结点上运行业界公认的NPB测试程序,结果显示32个结点中ATC的平均命中率达到了95.3%,表明ATC设计的正确性与高性能.并且通过与3种传统SRAM(static random access memory)实现的cache进行对比实验,说明了cache容量是提高命中率的关键因素.
[Abstract]:At present, in large-scale parallel computers, most users of parallel programs are accustomed to using virtual addresses for programming. Therefore, the efficiency of translation between virtual address and physical address directly affects the execution performance of parallel programs, while cache can effectively improve the efficiency of virtual and real address translation and reduce the delay. In this paper, an address translation cachein large scale parallel computer interconnection network is proposed. It uses embedded DRAM(embedded dynamic random access memory memory DRAM memory to accommodate more address translation table items, thus improving hit rate. A eDRAM refresh mechanism is designed, which hides the refresh operation and avoids the performance loss caused by the refresh. ATCU address translation cache) implements a variety of reliability designs such as error-correcting code and bypass mechanism. Running the recognized NPB test program on 32 computing nodes, the results show that the average hit rate of ATC in 32 nodes is up to 95.3, which indicates the correctness and high performance of ATC design. By comparing with three kinds of cache realized by traditional SRAM(static random access memory, it is proved that cache capacity is the key factor to improve hit rate.
【作者单位】：国防科学技术大学计算机学院;
【基金】：国家自然科学基金项目(61103083,61133007) 国家“八六三”高技术研究发展计划基金项目(2012AA01A301) 国家“九七三”重点基础研究发展计划基金项目(2011CB309705)~~
【分类号】：TP333

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