一种高性能DSP芯片中寄存器文件的设计与实现

发布时间：2018-05-06 22:03

本文选题：寄存器文件 + 全定制　；参考：《哈尔滨工业大学》2012年硕士论文

【摘要】：寄存器文件位于处理器内核中，且一般处于数据通路上，其性能的好坏直接关系到处理器的性能。尤其在一些关键应用场合对处理器的性能指标要求非常高，这就需要设计在面积、速度、功耗几个方面达到最优化的寄存器文件。本文的寄存器文件要应用在一款高性能DSP处理器上，根据处理器的结构确定了相应的设计要求，研究了多端口寄存器文件的全定制设计和实现技术，并采用了全定制的方法对其进行设计。在传统6管存储单元的基础上，对其进行修改，，添加了读写端口，消除了读破坏，并基于统计学的基础上，做出了反相读出的设计，减小了功耗的同时加快了读出数据的速度。对译码器的设计在分析了静态逻辑与动态逻辑的基础上决定采用两级动态译码，在速度与稳定性两者之间取得了很好的平衡。设计定向通路，这一电路结构的存在进一步优化了读操作。本文对版图设计的过程和一般技术进行了研究，在进行版图设计时，分别采用了手指状折叠技术、电源地共享、源漏共用等一系列技术减少了19%的版图面积。本文还对寄存器文件时序库的建立进行了研究和实现，为以后单元库的建立打下了良好的基础。采用Synopsys的Liberty NCX建库工具对设计进行了时序库的建立，在这过程当中介绍了时序信息的提取、时序弧的测量、采样点的选择等与建库紧密相关的知识。本文在65nm工艺下完成了一个具有10个读端口6个写端口，容量为32×32位、能够在单周期内完成数据写入并读出、含有定向通路的寄存器文件。该寄存器文件频率可以达到600MHz。
[Abstract]:The register file is located in the processor kernel and generally in the data path, and its performance is directly related to the processor performance. Especially in some key applications, the performance requirements of the processor are very high, which requires the design of the optimal register file in area, speed and power consumption. The register file in this paper should be applied to a high-performance DSP processor. According to the structure of the processor, the corresponding design requirements are determined, and the full customization design and implementation technology of the multi-port register file is studied. The method of full customization is used to design it. On the basis of the traditional 6-transistor memory cell, we modify it, add the read and write port, eliminate the reading damage, and based on statistics, we make the design of inverse readout, which reduces the power consumption and speeds up the readout speed. The design of the decoder is based on the analysis of static logic and dynamic logic, and it is decided to adopt two-stage dynamic decoding, which achieves a good balance between speed and stability. By designing the directional path, the existence of this circuit structure further optimizes the read operation. In this paper, the process and general technology of layout design are studied. In the process of layout design, a series of techniques, such as finger folding, power sharing and source-drain sharing, are used to reduce the layout area by 19%. In this paper, the establishment of register file timing library is also studied and implemented, which lays a good foundation for the establishment of unit library in the future. In this paper, the time sequence database is built by using the Liberty NCX database tool of Synopsys. In the process, the extraction of time sequence information, the measurement of sequential arc, the selection of sampling points and so on are introduced, which are closely related to the construction of the database. In this paper, a register file with 10 read ports and 6 write ports, with capacity of 32 脳 32 bits, can be written and read out in a single cycle under 65nm technology. The frequency of the register file can reach 600 MHz.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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