DSP片内多通道缓冲串行接口的设计与研究

发布时间：2018-05-09 11:44

本文选题：串行接口 + 多通道缓冲串口　；参考：《东南大学》2016年硕士论文

【摘要】：近年来,随着集成电路技术的迅猛发展,处理器和内存性能的飞速提高,处理器内部以及处理器之间的数据交互的频率和交互的数据量也在高速增长,这就对数据传输的效率提出了更高的要求。McBSP (Multichannel Buffered Serial Port,多通道缓冲串行接口)既可以实现时分多路串行通信功能,又可以通过DSP提供的DMA总线连接实现不通过CPU直接进行自动缓存功能,从而使得DSP能够从繁重的串口通讯任务中解放出来,提高了DSP的整体运行速率。本论文主要以多通道缓冲串行接口为研究主题,深入分析了目前国内外的发展趋势,研究了SPI(Serial Peripheral Interface,串行外设接口)总线接口,中断,μ律和A律压缩的相关技术,完成了多通道缓冲串行接口的设计。本文阐述了McBSP的整体功能、性能和结构,说明了McBSP的基本工作流程,详细描述了McBSP每个功能模块的具体设计。针对当使用McBSP压扩芯片内部数据时,CPU或DMA控制器无法监控接收和发送中断或同步事件的变化,若全程使用轮询方式监控这些变化则会影响数据的读写速率这一问题,增加数字环回模式(DLB)与非数字环回模式(非-DLB)的选择。针对于有时同时进行多个数据单元的读写操作的需求,加入了多通道选择模块。在验证方面,运用Xilinx的开发工具搭建测试平台,呈现了平台搭建的整个过程,对本设计的McBSP模块系统进行了7种基本的测试,包括时钟与帧同步配置验证、中断处理能力验证、数据压缩处理能力验证、通道选择验证、帧同步忽略验证、数据发送与接收验证、SPI接口兼容性验证,确保McBSP模块功能的准确性。在Xilinx公司的Virtex7系列开发板上对设计进行验证,验证结果表明本文设计的McBSP串行接口支持串行数据读写操作,支持中断操作,支持全双工的数据传输模式,支持数据压缩模式传输,支持多通道选择,支持SPI协议,最高时钟频率可达到260.281MHz.经过测试平台的验证,论文设计的McSBP模块功能完善,性能可靠,己完全达到设计的功能和性能要求,可以在DSP片内进行使用。
[Abstract]:In recent years, with the rapid development of integrated circuit technology and the rapid improvement of processor and memory performance, the frequency of data interaction and the amount of data between processors are also growing rapidly. This puts forward higher requirements for the efficiency of data transmission. McBSP / Multichannel Buffered Serial (multi-channel buffering serial interface) can realize the function of time-division and multi-channel serial communication. The DMA bus connection provided by DSP can also realize the function of automatic cache without CPU, thus DSP can be freed from the heavy serial communication task, and the overall running rate of DSP can be improved. In this paper, the multi-channel buffer serial interface is the main research topic, and the development trend at home and abroad is deeply analyzed, and the related technologies of SPI(Serial Peripheral interface, interrupt, 渭 law and A law compression are studied. The design of multi-channel buffer serial interface is completed. This paper describes the whole function, performance and structure of McBSP, explains the basic workflow of McBSP, and describes the design of each function module of McBSP in detail. In view of the fact that McBSP or DMA controller can not monitor the changes of receiving and sending interrupt or synchronous events when the internal data of McBSP is used, the rate of reading and writing of data will be affected if the changes are monitored by polling. The selection of digital loop mode (DLB) and non-digital loop mode (non--DLB) is added. To meet the need of reading and writing of multiple data units at the same time, a multi-channel selection module is added. In the aspect of verification, using the development tools of Xilinx to build the test platform, the whole process of the platform is presented. The McBSP module system designed in this paper has carried out seven basic tests, including clock and frame synchronization configuration verification, interrupt processing ability verification. Data compression processing capability verification, channel selection verification, frame synchronization ignoring verification, data sending and receiving verification and compatibility verification of SPI interface ensure the accuracy of McBSP module function. The design is verified on the Virtex7 series development board of Xilinx Company. The result shows that the McBSP serial interface designed in this paper supports serial data reading and writing operation, interrupt operation and full duplex data transmission mode. It supports data compression mode transmission, multi-channel selection and SPI protocol. The highest clock frequency can reach 260.281 MHz. After verification of the test platform, the McSBP module designed in this paper has perfect function and reliable performance, which can be used in DSP chip.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP334.7;TP332

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