基于CPCI平台的PCIE总线高速交换背板设计与实现

发布时间：2018-05-12 13:41

本文选题：PCIE + 信号完整性　；参考：《北京邮电大学》2013年硕士论文

【摘要】：随着微处理器技术、多媒体技术与网络技术的迅速发展,海量数据传输与交换对系统带宽的需求越来越高。传统的并行总线带宽已不能满足当前系统的需求,取而代之的是以PCIE为核心的第三代高速串行总线。PCIE总线采用点对点基于报文交换的数据传输方式,具有出色的电气性能。同时,CPCI平台因具有高开放性、高可靠性、可热插拔、易于加固和低成本等优势而获得广泛应用。但CPCI平台采用PCI总线作为其数据传输通道,其传输带宽的限制,严重阻碍了CPCI平台在高速率、高带宽领域的发展。本文针对PCI总线带宽的不足,将PCIE总线引入CPCI平台,完成CPCI平台下PCIE总线高速交换背板的研制。首先分析了CPCI平台下PCIE信号互连引起的信号完整性、电源完整性、电磁兼容等关键问题。其次根据PCIE总线拓扑结构的特点,进行了PCIE整体交换架构和各功能模块的详细设计,完成了高速交换背板的PCB叠层、布局、布线,在设计中采用传输线理论+PCIE布线规范+EDA仿真相结合的方法,有效控制了PCIE信号在PCB板与高速连接器上传输时的信号完整性。最后通过对PCIE总线高速交换背板的性能指标进行测试,每一条PCIE数据链路可提供1.5Gbps的带宽,背板整体交换能力达到7.5Gbps,验证了方案的正确性与可行性。本文将PCIE信号引入CPCI平台,可解决CPCI平台中差异化设备板卡接入时PCI总线与PCIE总线共存的问题。因背板具有大容量交换的性能,系统可用于电信设备、网络通讯、工业控制、航空航天、军事装备等对设备机械性能和电气性能要求较高的领域。同时也为其他高速串行总线引入CPCI平台提供一定的参考。此外,对其他高速信号在CPCI背板中互连也有一定的参考价值。
[Abstract]:With the rapid development of microprocessor technology, multimedia technology and network technology, the demand of mass data transmission and exchange for system bandwidth is increasing. The traditional parallel bus bandwidth can no longer meet the needs of the current system. Instead, the third generation high-speed serial bus, .PCIE, which takes PCIE as the core, adopts a point-to-point data transmission mode based on message exchange, which has excellent electrical performance. At the same time, CPCI platform has been widely used because of its advantages of high openness, high reliability, hot pluggable, easy reinforcement and low cost. However, the CPCI platform uses PCI bus as its data transmission channel. The limitation of its transmission bandwidth seriously hinders the development of CPCI platform in the field of high speed and high bandwidth. Aiming at the shortage of PCI bus bandwidth, this paper introduces PCIE bus into CPCI platform, and completes the development of PCIE bus high speed switch backplane based on CPCI platform. Firstly, the signal integrity, power supply integrity and electromagnetic compatibility caused by PCIE signal interconnection on CPCI platform are analyzed. Secondly, according to the characteristics of PCIE bus topology, the PCIE switching architecture and each functional module are designed in detail, and the PCB stack, layout and wiring of the high-speed switching backplane are completed. In the design, the transmission line theory PCIE routing specification EDA simulation method is used to effectively control the signal integrity of PCIE signal transmitted on PCB board and high speed connector. Finally, by testing the performance index of PCIE bus high-speed switching backplane, each PCIE data link can provide the bandwidth of 1.5Gbps, and the overall switching capability of backplane reaches 7.5 Gbps. the correctness and feasibility of the scheme are verified. In this paper, the PCIE signal is introduced into the CPCI platform, which can solve the problem of the coexistence of PCI bus and PCIE bus when the differential device card is connected in the CPCI platform. Because the backplane has the capability of large capacity exchange, the system can be used in the fields of telecommunication equipment, network communication, industrial control, aerospace, military equipment and so on, which require higher mechanical and electrical performance of the equipment. At the same time, it also provides some reference for other high speed serial bus to introduce CPCI platform. In addition, it has some reference value for other high-speed signals interconnecting in CPCI backplane.
【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336

【参考文献】