基于NAND Flash的嵌入式图像记录技术

发布时间：2018-05-15 23:33

本文选题：NAND + Flash阵列　；参考：《中国科学院研究生院（光电技术研究所）》2013年博士论文

【摘要】：NAND Flash具有功耗低、体积小、重量轻、固态化、发热少、抗震能力强、工作温度宽等优点，非常适合用来设计使用环境严酷的超高速图像记录系统。本文针对基于NAND Flash设计记录系统存在的一系列关键技术问题，，分别提出和实现了满足高性能要求的系统架构和数据流控制算法。针对如何提高NAND Flash物理底层访问速度问题，研究了NAND Flash的内部结构和工作原理，分析了各类操作的物理底层驱动逻辑。在FPGA中分别实现了操作NAND Flash的各种时序。从理论层面研究了传统的片外流水线和并行技术，并提出了片外两级流水和内部交叉写入结合的方法。通过FPGA硬件实现，证明了本文提出的方法具有最大流水线加速比，能有效提高写入速度，同时减少了FPGA引脚资源占用。针对坏块表的快速检索和可靠存储问题，提出了基于位索引的坏块信息快速检索结构；为解决坏块快速匹配问题，提出了基于滑动窗口的无效块预匹配机制；对于突发坏块造成写入速度下降问题，提出了滞后回写机制。坏块管理全部用硬件实现；提出并实现了一种高效的并适合于顺序数据流记录的损耗均衡方法。同时提出和实现了一种NAND Flash扩展方法，能有效避免NAND Flash记录系统要使用多个NAND Flash控制器的情况，节省了FPGA内部资源；针对嵌入式超高速图像记录应用中，任务如何有效管理的问题，设计了超高速图像数据流内存缓存机制，实现了高带宽图像数据缓存和任务附加信息实时嵌入。提出了一种两级数据索引机制，并详细阐述了任务管理的映射关系。为保证记录数据的安全性，实现了任务管理相关表项在NOR Flash中的备份和定时更新机制。实践表明，以上方法能够有效降低CPU开销，适合在嵌入式系统中应用。针对记录系统性能测试问题，设计了测试模型，包括：针对系统可靠性初步测试问题，设计了基于指数回归的速度压力模型和基于对数正态分布的测试时长控制模型；针对峰值记录速度测定问题，提出了基于爬山搜索算法和速率二分法的软硬件协同测试方法。通过FPGA实现，验证了提出方法的有效性。为了推进相关研究成果的工程实用化，设计并实现了光电经纬仪NANDFlash嵌入式图像记录系统。分别研究和实现了光纤、PCIE、千兆网传输、DVI显示回放以及基于WEB服务器的记录系统远程管理技术。结果表明，该系统最大记录带宽可达1260MB/s，容量可达8TB；最后，研究了结构紧凑多模块记录系统，设计了3U CPCIE记录模块。该系统可根据具体需求增加和裁剪记录模块，实现不同的记录性能。
[Abstract]:NAND Flash has the advantages of low power consumption, small volume, light weight, solid state, less heating, strong seismic ability, wide working temperature, etc., so it is very suitable for designing ultra-high speed image recording system with harsh environment. Aiming at a series of key technical problems existing in the design of recording system based on NAND Flash, this paper proposes and implements the system architecture and data flow control algorithm which meet the requirements of high performance respectively. Aiming at the problem of how to improve the access speed of physical bottom layer of NAND Flash, the internal structure and working principle of NAND Flash are studied, and the physical underlying driving logic of all kinds of operations is analyzed. All kinds of timing of NAND Flash operation are realized in FPGA. In this paper, the traditional off-chip pipeline and parallel technology are studied theoretically, and the method of combining two-stage pipeline and internal cross-writing is proposed. Through the implementation of FPGA hardware, it is proved that the proposed method has the maximum pipeline speedup ratio, can effectively improve the write speed and reduce the FPGA pin resource consumption. In order to solve the problem of fast retrieval and reliable storage of bad block table, a fast retrieval structure of bad block information based on bit index is proposed, and an invalid block pre-matching mechanism based on sliding window is proposed to solve the problem of fast bad block matching. For the problem of slow down of writing speed caused by burst bad block, a delayed write-back mechanism is proposed. The bad block management is implemented by hardware, and an efficient loss equalization method suitable for sequential data stream recording is proposed and implemented. At the same time, a NAND Flash extension method is proposed and implemented, which can effectively avoid the use of multiple NAND Flash controllers in the NAND Flash recording system and save the internal resources of FPGA. Aiming at the problem of how to manage the task effectively in the application of embedded ultra high speed image recording, a memory cache mechanism of super high speed image data stream is designed, which realizes the high bandwidth image data cache and the real time embedding of task additional information. A two-level data indexing mechanism is proposed and the mapping relationship of task management is described in detail. In order to ensure the security of recording data, the backup and timing updating mechanism of task management related table items in NOR Flash is implemented. Practice shows that the above method can effectively reduce the CPU overhead and is suitable for application in embedded systems. Aiming at the problem of recording system performance test, the test model is designed, including: aiming at the system reliability preliminary test problem, the speed pressure model based on exponential regression and the test time control model based on logarithmic normal distribution are designed. In order to solve the problem of peak recording speed measurement, a software / hardware co-testing method based on mountain climbing search algorithm and rate dichotomy is proposed. The effectiveness of the proposed method is verified by FPGA implementation. In order to promote the engineering practicability of related research results, an embedded image recording system for photoelectric theodolite NANDFlash is designed and implemented. The technologies of optical fiber PCIEs, Gigabit network transmission DVI display and playback and remote management of recording system based on WEB server are studied and implemented respectively. The results show that the maximum recording bandwidth of the system can reach 1260 MBs and the capacity can reach 8 TB.Finally, the compact multi-module recording system is studied, and the 3U CPCIE recording module is designed. The system can add and cut the recording module according to the specific requirements to achieve different recording performance.
【学位授予单位】：中国科学院研究生院（光电技术研究所）
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP333;TP391.41

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