高性能浮点加法器的研究与设计

发布时间：2018-05-17 06:35

本文选题：浮点加法 + 双通道算法　；参考：《南京航空航天大学》2012年硕士论文

【摘要】：随着信息应用领域对数据运算精度要求的不断提高和数值运算范围的不断扩大，现代微处理器中，浮点运算单元（Floating-point Unit，FPU）的研究显得越来越重要。根据相关技术报告，浮点运算中55%以上是浮点加法运算。因此，浮点加法是使用频率最高的浮点运算，浮点加法器也成为微处理器、现代信号处理系统中最重要的部件之一。IEEE-754标准中浮点数定义的复杂性使得硬件实现浮点加法操作的速度远低于定点数。本文在传统浮点加法器串行计算结构的基础上，讨论了并行计算的双通道算法，改进的双通道算法等结构。在双通道结构中，，分析研究前导1（前导0）预测算法，桶形移位器等关键结构和模块。在深入研究和分析这些关键结构和模块之后，总体上确定了以双通道算法为本文所设计的浮点加法器的结构。在前导1预测的模块中，以预编码逻辑为基础，对预编码进行前导1检测。此外，移位器使用纯组合逻辑电路的桶形移位器，以避免使用移位寄存器逻辑电路所带来的延时。定点加法器作为浮点加法运算中不可或缺的模块之一，很大程度上制约着浮点加法器的性能。本文在定点加法器部分，在传统并行前缀加法器原有的结构基础上，介绍了一种高速的Ling进位加法器，并且提出了一种基于Ling加法器的逻辑电路层次结构上的改进的加法器。实验数据表明，本文设计的改进32位Ling加法器比传统32位并行前缀Ling加法器延时降低了约18%，同时面积上也减小了20%左右。本文使用一个24位的改进Ling加法器用于浮点加法器的尾数运算模块中，使得优化后的浮点加法器延时进一步减小。论文完成了浮点加法器从体系结构选择、算法研究到可综合的代码编写、仿真综合等一系列工作。所有的设计均使用VerilogHDL语言作为设计输入，所有的数据均在Synopsys的DC下进行综合得到。实验结果表明，本文设计的浮点加法器可以高效地、正确地完成浮点加法运算，达到了预期的目标。
[Abstract]:With the improvement of the precision of data operation and the expansion of numerical operation range in the field of information application, the research of floating-point unit (Floating-point unit FPU) is becoming more and more important in modern microprocessors. According to relevant technical reports, more than 55% of floating-point operations are floating-point addition operations. Therefore, floating-point addition is a floating-point operation with the highest frequency, and the floating-point adder becomes a microprocessor. The complexity of floating-point definition in IEEE-754 standard makes the speed of floating-point addition in hardware much lower than the number of fixed points. Based on the serial computing structure of the traditional floating-point adder, this paper discusses the two-channel algorithm for parallel computing and the improved two-channel algorithm for parallel computing. In the dual channel structure, the key structures and modules, such as preamble 1 (lead 0) prediction algorithm, bucket shifter and so on, are analyzed and studied. After deeply studying and analyzing these key structures and modules, the structure of the floating-point adder designed in this paper based on the two-channel algorithm is determined. In the precoding 1 prediction module, precoding logic is used to detect the precoding. In addition, the shifter uses a bucket shifter of pure combinational logic circuits to avoid the delay caused by the use of shift register logic circuits. As one of the indispensable modules in floating-point addition, fixed-point adder restricts the performance of floating-point adder to a great extent. In the part of fixed-point adder, this paper introduces a high-speed Ling carry adder based on the original structure of traditional parallel prefix adder, and proposes an improved adder based on Ling adder in logic circuit hierarchy. The experimental data show that the improved 32-bit Ling adder can reduce the delay time by about 18% and reduce the area by about 20% compared with the traditional 32-bit parallel prefix Ling adder. In this paper, a 24-bit improved Ling adder is used in the Mantissa calculation module of the floating-point adder, which further reduces the delay of the optimized floating-point adder. In this paper, a series of tasks, such as architecture selection, algorithm research, compositive coding, simulation synthesis and so on, are completed. All the designs use VerilogHDL language as the design input, and all the data are synthesized under the DC of Synopsys. The experimental results show that the floating-point adder designed in this paper can accomplish floating-point addition efficiently and correctly, and achieve the desired goal.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.21

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