高性能微处理器门控电源设计技术研究

发布时间：2018-05-19 18:40

  本文选题：微处理器 + 低功耗　； 参考：《国防科学技术大学》2013年硕士论文

【摘要】：随着高性能微处理器进入多核多线程处理器设计时代,集成电路生产工艺发生翻天覆地的变革,传统的摩尔定律受到前所未有的挑战,功耗问题成为制约处理器发展的首要问题之一。尤其在集成电路制造工艺进入90nm工艺尺寸后,漏流功耗问题愈发突出,传统的低功耗技术不能有效控制漏流功耗,因此新的低功耗技术应运而生。本文通过对X微处理器代码进行研究,分析处理器结构功能,在此基础上为X微处理器增加门控电源设计以降低处理器功耗。设计针对处理器核心的粗粒度门控电源,在不需要某些处理器核工作时关闭处理器核电源。设计了一个功耗管理控制单元PMC来完成处理器核上下电流程的控制。研究门控电源技术的验证方法,并提出电源开关的后端设计方案。设计针对处理器SRAM的细粒度门控电源,提出一种硬件动态控制的门控电源设计方案。本文首先为处理器合理划分电源域,设计电源模式,完成门控电源整体方案设计。通过编写CPF通用低功耗格式文件将设计方案施加在处理器上,并针对X微处理器核工作特点设计核心上下电流程方案。通过模拟验证说明低功耗意图已成功部署在处理器上。根据处理器结构特点,为实现上下电流程的自动控制本文设计了功耗管理控制单元PMC。具体介绍了PMC的设计方案,分析其结构组成、工作原理和内部状态转换,并编写verilog代码实现设计。最后通过编写测试激励,将CPF文件同X微处理器代码一起进行模拟测试。通过观察波形验证了PMC设计功能的正确性,能够起到正确控制核心打开和关断的作用。最后本文阐述了门控电源设计的验证方法,结合布局布线相关技术,提出了门控电源网络设计方法。通过对多种不同的门控电源开关结构进行分析对比,使用RedHawk软件测试不同结构的电源开关和不同链间上电间隔的电源开关对瞬态电流的影响,最后提出一种测试效果较好的四条链并联结构的电源开关结构。另外,本文针对X处理器中的一级指令cache提出了硬件动态控制的细粒度电源门控技术,利用指令队列进行程序中循环代码的检测。一旦检测到循环代码,就可以对指令cache进行电源门控,从而降低动态功耗和静态功耗。模拟实验数据表明,该方法不但可以降低动态功耗和静态功耗,还可以小幅度提升性能。
[Abstract]:With the entry of high-performance microprocessors into the era of multi-core multi-thread processor design, the production process of integrated circuits has undergone world-shaking changes, the traditional Moore's law has been unprecedented challenges. Power consumption has become one of the most important problems restricting the development of processors. Especially after the IC manufacturing process enters the 90nm process size, the leakage power problem becomes more and more prominent. The traditional low-power technology can not effectively control the leakage power consumption, so the new low-power technology emerges as the times require. In this paper, the code of X microprocessor is studied, and the structure and function of the processor are analyzed. On this basis, the design of gated power supply for X microprocessor is added to reduce the power consumption of the processor. A coarse-grained gated power supply for processor core is designed to turn off processor core power when some processor cores are not needed. A power management control unit (PMC) is designed to control the power flow of the processor core. The verification method of gated power supply technology is studied, and the back end design scheme of power switch is proposed. A hardware dynamic control scheme for a fine-grained gated power supply for processor SRAM is proposed. Firstly, this paper divides the power domain reasonably for the processor, designs the power supply mode, and completes the whole scheme design of the gated power supply. The design scheme is applied to the processor by writing the CPF general low power format file, and the core charging flow scheme is designed according to the working characteristics of the X microprocessor core. Simulation verification shows that the low power intention has been successfully deployed on the processor. According to the characteristics of processor architecture, a power management control unit (PMC) is designed to realize the automatic control of power flow. This paper introduces the design scheme of PMC, analyzes its structure, working principle and internal state transformation, and writes verilog code to realize the design. Finally, the CPF file and X microprocessor code are simulated and tested by writing test incentives. The function of PMC design is verified by observing the waveform, which can control the opening and closing of the core correctly. Finally, this paper describes the verification method of the gated power supply design, and puts forward the design method of the gated power supply network based on the layout and wiring technology. Through the analysis and comparison of many different switch structures, the influence of the power switch with different structure and the power switch between the different chains on the transient current is tested by using RedHawk software. Finally, a power switch structure with four chains parallel structure is proposed. In addition, this paper presents a fine-grained power gating technique for the first-order instruction cache in X processor, which is dynamically controlled by hardware. The instruction queue is used to detect the cyclic code in the program. Once the cyclic code is detected, the instruction cache can be power gated to reduce the dynamic and static power consumption. The simulation results show that the proposed method can not only reduce dynamic and static power consumption, but also improve performance by a small margin.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
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本文编号：1911207