YHFT-DSPX中PCI接口部件的设计与实现

发布时间：2018-05-20 17:15

本文选题：PCI接口 + PCI2.2协议　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：YHFT-DSPX是我校自主设计的新一代高性能32位定点DSP微处理器芯片，在无线基站、ADSL、雷达、图像及多媒体信息处理等高性能数字信号处理方面应用前景广泛。本文为YHFT-DSPX设计实现了一款32位的PCI接口，以增强DSP与外部主机以及与外围控制部件的数据传输能力，为DSP与主机之间的数据通信提供了快速通道。本文深入分析PCI接口的功能特点，按YHFT-DSPX系统要求完成了PCI接口的设计验证和FPGA仿真。所设计的PCI接口部件基于PCI2.2总线协议并满足PC99规范要求，总线宽度32位，PCI工作频率33MHz，最高传输带宽可达132MB/s。接口支持存储器读、存储器一行读、存储器多行读、存储器写、IO读、IO写、配置寄存器读以及配置寄存器写等PCI总线命令。接口可作为发起总线事务主设备也可作为接受总线事务的从设备。接口具备自动初始化功能：外接EEPROM存储器，在PCI接口上电复位后，EEPROM控制器用ROM中存储的配置信息自动完成PCI接口的初始化配置。接口内部通过DMA传输和DSP连接，使用多个并行的FIFO来保证接口的高速数据传输。另外，PCI接口内部有专门的寄存器文件通道和DSP连接，方便DSP和PCI接口之间进行状态信息和控制命令的交互。最后论文对PCI接口部件采用65nm标准单元工艺库进行了综合，，接口内部时钟最高工作频率可以达到555MHz。按照系统最低400MHz的内部时钟工作频率要求，PCI接口综合结果面积为61781um~2，功耗为3.1696mW。符合系统设计要求。
[Abstract]:YHFT-DSPX is a new generation of high performance 32-bit fixed-point DSP microprocessor designed by our university. It has a wide application prospect in wireless base station, radar, image and multimedia information processing and other high-performance digital signal processing. In this paper, a 32-bit PCI interface is designed and implemented for YHFT-DSPX to enhance the ability of data transmission between DSP and external host and peripheral control components, and to provide a fast channel for data communication between DSP and host. In this paper, the functional characteristics of PCI interface are deeply analyzed, and the design and verification of PCI interface and FPGA simulation are completed according to the requirements of YHFT-DSPX system. The designed PCI interface is based on the PCI2.2 bus protocol and meets the requirements of the PC99 specification. The bus width is 32 bits and the operating frequency is 33MHz. The maximum transmission bandwidth can be up to 132MB / s. The interface supports memory reading, memory line reading, memory multiline reading, memory writing IO reading, configuration register writing and other PCI bus commands. The interface can act as the host device for initiating a bus transaction or as a slave device for receiving a bus transaction. Interface has the function of automatic initialization: external EEPROM memory, after the PCI interface power reset, the EEPROM controller automatically completes the initialization configuration of PCI interface with the configuration information stored in ROM. The interface is connected by DMA and DSP, and multiple parallel FIFO are used to guarantee the high speed data transmission of the interface. In addition, there is a special register file channel and DSP connection inside the interface, which facilitates the exchange of state information and control commands between DSP and PCI interface. Finally, the 65nm standard cell process library is used to synthesize the PCI interface components. The highest working frequency of the internal clock can reach 555MHz. According to the minimum internal clock frequency of the system, the integrated result area of 400MHz interface is 61781 umm2, and the power consumption is 3.1696 MW. Meet the system design requirements.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7

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