低功耗浮点乘加部件的研究与优化

发布时间：2018-05-21 09:50

本文选题：浮点乘加部件 + 低功耗　；参考：《北京邮电大学》2012年硕士论文

【摘要】：浮点乘加部件(Multiply-Add Fused, FMA)是高性能微处理器中的核心运算部件之一,它的速度与功耗对整个微处理器性能具有很大的影响。随着应用技术对低功耗的要求不断增加,研究低功耗的浮点乘加部件的算法和设计优化技术,实现高性能低功耗的浮点乘加部件具有广泛的应用价值和重要的现实意义。乘加不仅具有面积大、延迟长、功耗高的特点,特别是浮点乘加部件。如何从延迟、面积和功耗三个方面综合考虑乘法器设计是本文讨论的重点。论文主要从浮点乘加联合部件的结构,门级和电路级着手,研究和优化,以实现其低功耗。主要取得了以下几方面的工作成果。 1.编码是快速乘法运算的基础；考虑到编码结果对乘法电路翻转概率的影响,比较了乘法器的各种编码方式之后,选择了一种低功耗Booth编码方法。 2.部分积累加的过程是乘加运算中占用资源最多的一个部分。本文分析了CSA3：2压缩器和二叉树4：2压缩器等,设计了一种4：2压缩器,在面积,功耗方面都有很大提升。 3.前导0预测算法设计是高性能浮点乘加部件设计的重要一部分。本文的主要工作是提出了一种新的前导0预测错误纠正算法,该算法通过对传统非精确预测算法的结果进行并行地错误修正,从而实现了精确的前导0预测逻辑,并且与已有算法相比,该算法具有功耗和面积方面的较明显优势。 4.在本文中提出一种新的乘法器的架构以实现其低功耗设计,从架构级,把乘法电路分成更小的乘法器群组,减小电路的切换活动,进而实现减小功耗的目的。应用门控时钟技术和对输入数据进行预处理操作,使用Candence软件,采用0.18微米技术,测试中,所有可能的输入组合具有相同的概率。SPICE测试结果表明,这种结构可以节约功耗达13.36%
[Abstract]:Floating-point multiplicative component (FMA) is one of the core computing components in high performance microprocessors. Its speed and power consumption have great influence on the performance of the whole microprocessor. With the increasing demand of application technology for low power consumption, it is of great value and practical significance to study the algorithm and design optimization technology of low power floating-point multiplicative and additive components, and to realize high performance and low-power floating-point multiplicative and additive components with high performance and low power consumption. Multiplicative addition is characterized by large area, long delay and high power consumption, especially floating-point multiplicative components. How to synthetically consider multiplier design from three aspects of delay, area and power consumption is the focus of this paper. This paper studies and optimizes the structure, gate level and circuit level of floating-point multiplicative plus joint component to realize its low power consumption. The main achievements are as follows. 1. Coding is the basis of fast multiplication, considering the effect of coding result on the probability of multiplication circuit, a low power Booth coding method is selected after comparing various coding methods of multiplier. 2. The process of partial accumulation and addition is one of the most resource-consuming parts in multiplication and addition operations. In this paper, the CSA3:2 compressors and the 4:2 binomial tree compressors are analyzed, and a 4:2 compressor is designed, which can greatly improve the area and power consumption. 3. The design of leading 0 prediction algorithm is an important part of the design of high performance floating-point multiplication plus components. The main work of this paper is to put forward a new error correction algorithm of leading 0 prediction. The algorithm implements accurate prediction logic by correcting the results of traditional inexact prediction algorithm in parallel. Compared with the existing algorithms, this algorithm has obvious advantages in power consumption and area. 4. In this paper, a new multiplier architecture is proposed to realize its low power design. From the architecture level, the multiplier circuit is divided into smaller multiplier groups, which reduces the switching activity of the circuit, and then realizes the purpose of reducing power consumption. By using gated clock technology and pretreatment of input data, using Candence software and 0.18 micron technology, all possible input combinations have the same probability. Spice test results show that this structure can save 13.36% power consumption.
【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.22

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