基于片上多核系统高速数据交换接口的关键技术研究

发布时间：2018-05-23 11:51

本文选题：交换接口 + 网络处理器　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：随着网络系统的高速发展，，作为网络系统的核心设备网络处理器也得到了高速的发展，高速数据交换接口的性能是网络处理器处理网络数据包和影响网络处理器性能的关键因素之一，而且它和MAC芯片之间的交换接口性能决定着网络处理器最大的数据吞吐能力，所以设计实现网络处理器中高速数据交换接口对于提升整个网络的性能就显得意义特别重大。本文重点研究了网络处理器中高速数据交换接口的几点关键技术的解决方案。为了实现MAC设备与网络处理器之间数据包的高速传输，将不需要微处理引擎处理的数据包净荷部分通过DMA通道存储到片外SDRAM存储器；MAC芯片和网络处理器的通信由于工作频率或者相位的不同，采用双口SRAM存储器作为数据缓存；为了保证发送数据的可靠性，采用两个有效标志位置位的方式确保数据能够高效可靠的发送到外部MAC设备；当高速数据交换接口与外接10/100M的MAC设备进行通信时，采用轮询的方式来获取MAC设备中FIFO数据的就绪状态；当高速数据交换接口与1000M的MAC设备进行通信时，采用主动请求机制接收数据包。对高速数据交换接口采用自顶向下的方法进行具体的设计，通过模块划分完成结构设计，对每个模块的具体特点进行详细描述，使用Verilog硬件描述语言完成高速数据交换接口的RTL级设计。对常用的验证方法进行介绍，并对设计的高速数据交换接口进行功能验证，然后给出适合本设计的验证方案，在此方案的基础上通过对需要验证的各项功能进行一致性对比，通过一套较完善的手段来检查设计的功能正确性。制定了性能评估方案，介绍性能测试的方法，然后对性能测试结果进行评估，最后对高速数据交换接口进行逻辑实现。得到了高速数据交换接口的面积和最大工作频率。
[Abstract]:With the rapid development of network system, network processor, the core device of network system, has also been developed rapidly. The performance of high-speed data exchange interface is one of the key factors for network processor to process network data packets and affect the performance of network processor. Moreover, the performance of switching interface between network processor and MAC chip determines the maximum data throughput of network processor. So it is very important to design and implement the high-speed data exchange interface in the network processor to improve the performance of the whole network. This paper focuses on the solution of several key technologies of high-speed data exchange interface in network processor. In order to realize the high-speed transmission of data packets between MAC devices and network processors, The data packet payload part which does not need to be processed by the micro-processing engine is stored to the off-chip SDRAM memory DMA chip and the network processor through the DMA channel. Because of the different operating frequency or phase, the dual-port SRAM memory is used as the data cache. In order to ensure the reliability of transmitting data, two effective marking position bits are adopted to ensure that the data can be transmitted to external MAC devices efficiently and reliably. When the high-speed data exchange interface communicates with the 10 / 100m external MAC devices, The ready state of FIFO data in MAC devices is obtained by polling, and when the high-speed data exchange interface communicates with 1000M MAC devices, the active request mechanism is used to receive data packets. The top-down method is used to design the high-speed data exchange interface. The structure is designed by module partition, and the specific characteristics of each module are described in detail. Verilog hardware description language is used to complete the RTL level design of high speed data exchange interface. The common verification methods are introduced, and the function of the designed high-speed data exchange interface is verified. Then the verification scheme suitable for this design is given. On the basis of this scheme, the consistency of the functions that need to be verified is compared. Through a set of more perfect means to check the functional correctness of the design. The performance evaluation scheme is established, the method of performance testing is introduced, and the performance test results are evaluated. Finally, the logical implementation of the high-speed data exchange interface is carried out. The area and maximum working frequency of high speed data exchange interface are obtained.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7

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