低速串行通信总线IP软核的设计与实现

发布时间：2018-05-23 18:37

本文选题：串行通信总线 + IP核　；参考：《华中科技大学》2013年硕士论文

【摘要】：随着集成电路设计发展到系统级的设计阶段，以软硬件协同设计、IP核复用和超深亚微米技术为支撑的SoC设计已成为当今超大规模集成电路的发展方向。另一方面，串行通信总线以其结构简单、节省传输线、成本更低等优点在越来越多的芯片中得到应用。本文设计了三种最具代表型的串行总线的可复用IP软核，这符合SoC设计技术的发展方向，具有重要的实用价值。 1-Wire总线是Maxim全资子公司Dallas的一项技术，它采用单根信号线，同时传输时钟和数据；I~2C总线是Philips公司推出的一种串行总线，定义了两根双向信号线，并支持多主机系统；SPI总线是由Motorola公司推出的一种同步串行外围设备接口，只需要4条线就可以完成主、从设备全双工同步通信。本文首先分析对比了常见的几种串行通信总线并详细介绍了1-Wire、I~2C和SPI这三种串行总线的标准协议，接着分别详细叙述了三种IP软核的设计与实现过程。首先根据需求制定了IP核的设计目标，并结合协议特点定义了多个可配置参数以实现最大可复用性；接着采用自顶向下的设计方法进行模块划分和接口时序的定义；然后采用Verilog语言描述实现了IP核各模块的功能；最后在基于BFM的验证环境中进行功能验证，使用FPGA进行IP核原型验证，并在华宏-NEC0.35um工艺综合实现。设计的三种IP软核采用不同的传输协议，但接口统一，且具备多个可配置参数，，通用性和可复用性好，可以广泛地应用于不同需求的芯片中。
[Abstract]:With the development of integrated circuit design to the stage of system-level design, SoC design, which is supported by hardware / software co-design IP core reuse and ultra-deep sub-micron technology, has become the development direction of VLSI. On the other hand, serial communication bus has been applied in more and more chips because of its simple structure, low cost and saving transmission line. In this paper, three kinds of reusable IP soft cores of serial bus are designed, which accord with the development direction of SoC design technology and have important practical value. 1-Wire bus is a technology of Dallas, a wholly owned subsidiary of Maxim. It uses single signal line, transmits clock and data at the same time, is a serial bus developed by Philips Company, and defines two two-way signal lines. The SPI bus is a synchronous serial peripheral interface developed by Motorola. It only needs 4 lines to complete the master and slave full duplex synchronous communication. In this paper, several common serial communication buses are analyzed and compared, and the standard protocols of 1-WireWay I2C and SPI are introduced in detail. Then, the design and implementation of three kinds of IP soft cores are described in detail. Firstly, the design goal of IP core is defined according to the requirements, and several configurable parameters are defined according to the characteristics of the protocol to realize the maximum reusability, then the module partition and interface timing are defined by the top-down design method. Then the functions of each module of IP core are described and implemented by Verilog language. Finally, the function verification is carried out in the verification environment based on BFM, and the prototype verification of IP core is carried out by using FPGA, which is implemented comprehensively in Huahong-NEC0.35um process. The three kinds of IP soft core adopt different transmission protocols, but the interface is uniform, and it has many configurable parameters. It has good versatility and reusability, so it can be widely used in chips with different requirements.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN402

【参考文献】