多核系统中通用浮点处理器的研究与设计

发布时间：2018-05-23 23:08

本文选题：多核系统 + 片上网络　；参考：《合肥工业大学》2017年硕士论文

【摘要】：随着集成电路工艺和计算机技术的高速发展,传统的依靠超标量和超流水线来提高处理器性能的方法遇到了瓶颈,多核SoC(System on Chip,SoC)技术应运而生,处理器的发展方向已经从追求单核心更高主频变为追求更多的处理器核。NoC (Network on Chip)将并行计算技术和计算机网络应用于芯片中,在带宽、可扩展性和可靠性等方面具有较大优势,已经成为一种重要的处理器互联方式。数字通信、图像处理、科学计算等应用对数据处理的精度和实时性的要求越来越高,硬件系统需要具备很强的浮点运算能力。本文以课题组的多核系统架构为基础,在研究了多核处理器技术、片上网络技术和在线调试技术之后,设计了一款主要针对高密度计算领域的通用浮点处理器,并以通用浮点处理器为运算单元搭建了多核系统,加载了相关计算任务。论文的主要工作如下:首先,根据高密度计算领域的算法特征和功能要求,确定了通用浮点处理器的整体架构。为了应对数据密集型和计算密集型两类算法应用,通用浮点处理器分别支持存储、流和脉动三种运算模式,最大程度地提高了运算灵活性和效率。其次,确定了通用浮点处理器微控制器单元、寄存器组、存储单元、网络接口和在线调试单元等模块的具体结构和工作机制,实现了通用浮点处理器的RTL级设计。最后,基于片上网络和通用浮点处理器搭建了多核系统,通过加载向量计算任务、矩阵特征分解算法、矩阵乘运算和FFT运算验证了通用浮点处理器和多核系统的功能正确性、算法适应性和可调试性。
[Abstract]:With the rapid development of integrated circuit technology and computer technology, the traditional method of improving processor performance based on superscalar and superpipeline has met the bottleneck, and the multi-core SoC(System on chip SoC has emerged as the times require. The development direction of processor has changed from pursuing higher main frequency of single core to pursuing more processor core. NOC Network on Chip) applying parallel computing technology and computer network to chip, which has great advantages in bandwidth, expansibility and reliability, etc. It has become an important way to interconnect processors. The applications of digital communication, image processing and scientific calculation require more and more high precision and real-time performance of data processing. Therefore, the hardware system needs to have strong floating-point operation ability. Based on the multi-core system architecture of the research group, after studying the multi-core processor technology, the on-chip network technology and the on-line debugging technology, a general floating-point processor is designed, which is mainly aimed at the field of high-density computing. A multi-core system based on a general floating-point processor is built and the related computing tasks are loaded. The main work of this paper is as follows: firstly, according to the algorithm features and functional requirements in the field of high density computing, the overall architecture of the general floating point processor is determined. In order to cope with the application of data-intensive and computation-intensive algorithms, the general floating-point processor supports storage, stream and pulsation respectively, which improves the flexibility and efficiency of computation to the greatest extent. Secondly, the structure and working mechanism of the general floating point processor microcontroller unit, register group, memory unit, network interface and on-line debugging unit are determined, and the RTL level design of the general floating point processor is realized. Finally, a multi-core system based on on-chip network and general floating-point processor is built. The functional correctness of the common floating-point processor and multi-core system is verified by loading vector computing task, matrix eigenvalue decomposition algorithm, matrix multiplication operation and FFT operation. Algorithm adaptability and debugging.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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