基于NAND FLASH的多路并行存储系统的研究与实现

发布时间：2018-05-24 18:23

本文选题：NAND + FLASH　；参考：《国防科学技术大学》2011年硕士论文

【摘要】：随着信息技术的高速发展,用户对数据存储容量和速度的要求不断增加,大容量高可靠性存储系统的要求给存储领域带来了挑战,而传统计算机存储系统采用的机械磁盘设备由于存储量、I/O访问延迟等问题成为限制存储系统性能的瓶颈。与此同时闪存(FLASH)作为非易失性存储介质拥有读写速度快、数据非易失性好、存储容量大、无机械机制、制造成本低廉、良好并行性潜力等特征,经过逐步发展和多次技术变革,逐渐显露出其巨大的优势,受到了国内外学者以及工业界的关注,未来或将替代传统磁盘。本文设计并实现了一个基于NAND FLASH的多路并行存储系统,以FPGA开发板为实验平台,使用三星公司的大容量NAND FLASH芯片为存储单元构建立多路并行存储系统,实验表明该系统具有良好的并行性、高速、可靠、安全等特点。论文的主要工作和创新包括: 1.对FLASH的相关技术和FLASH存储的研究现状进行了详细研究并提出建立NAND FLASH存储系统的可能性,并分析了构建系统的优点以及会遇到的难题;通过对NAND FLASH芯片内部结构和接口详细研究,提出了研究多路并行存储系统的可行性和目标。 2.根据FLASH芯片的结构特点,设计了基于NAND FLASH的多路并行存储板卡,并以此板卡为基础硬件完成了存储系统的模块设计,包括主逻辑模块设计、ECC模块设计、交差开关模块设计、乱序发射模块设计。 3.实现了基于NAND FLASH的多路并行存储系统,完成了系统对数据读、写、删除等操作的仿真,并在FPGA实验开发板上保证了系统对数据存取的正常运行。通过FPGA实验平台对系统进行测试,在4*8G的FLASH卡上实现了600M+的存取速率。 4.针对大规模固态闪存系统引入多路并行技术带来的坏块问题,提出了一种高效坏块管理策略,采取并行存储坏块编码技术来节约坏块表存储空间,减少坏块处理功耗,同时采取坏块表重构处理技术有效解决了系统中的同位置坏块难题。对FLASH芯片的顺序命令模式进行理论研究,提出了基于乱序发射的FLASH命令执行模型,并设计了基于乱序发射的NAND FLASH存储控制器。
[Abstract]:With the rapid development of information technology, the requirement of data storage capacity and speed is increasing. The requirement of large capacity and high reliability storage system brings challenges to the storage field. The mechanical disk equipment used in the traditional computer storage system is a bottleneck to the performance of the storage system because of the storage capacity and the I / O access delay. At the same time flash memory as a non-volatile storage medium has the characteristics of fast reading and writing speed, good data non-volatile, large storage capacity, no mechanical mechanism, low manufacturing cost and good parallelism potential. It gradually shows its great advantage, and has attracted the attention of domestic and foreign scholars and industry, and will replace the traditional disk in the future. In this paper, a multi-channel parallel storage system based on NAND FLASH is designed and implemented. The FPGA development board is used as the experimental platform, and Samsung's large-capacity NAND FLASH chip is used to construct a multi-channel parallel storage system. Experiments show that the system has good parallelism, high speed, reliability and security. The main work and innovations of the thesis include: 1. The related technology of FLASH and the research status of FLASH storage are studied in detail, the possibility of establishing NAND FLASH storage system is put forward, and the advantages and difficulties of constructing NAND FLASH storage system are analyzed. Through the detailed study of the internal structure and interface of the NAND FLASH chip, the feasibility and goal of studying the multi-channel parallel memory system are put forward. 2. According to the structure characteristics of FLASH chip, a multi-channel parallel memory card based on NAND FLASH is designed, and the module design of the storage system is completed based on the card, including the design of main logic module and the design of alternating switch module. The design of random sequence emitter module. 3. A multi-channel parallel storage system based on NAND FLASH is implemented, and the system simulation of data reading, writing and deleting is completed, and the normal operation of data access is ensured on the FPGA experimental development board. The system is tested on the FPGA platform, and the 600m access rate is realized on the 4G FLASH card. 4. In order to solve the bad block problem caused by the introduction of multiplex parallel technology in large scale solid-state flash memory system, an efficient bad block management strategy is proposed, in which the memory space of bad block table is saved and the power consumption of bad block processing is reduced by adopting parallel memory bad block coding technology. At the same time, the bad block table reconstruction technology is adopted to solve the problem of the same location bad block effectively. In this paper, the sequential command mode of FLASH chip is studied theoretically, and a FLASH command execution model based on random sequence transmission is proposed, and a NAND FLASH memory controller based on random sequence transmission is designed.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2011
【分类号】：TP333

【引证文献】