组合式伪随机数发生器的研究与设计

发布时间：2018-05-25 03:00

本文选题：伪随机数发生器 + 超素数发生器　；参考：《哈尔滨工程大学》2013年硕士论文

【摘要】：伪随机数发生器在计算机仿真和信息安全领域都有着广泛的用途，伪随机数序列的随机性、不可预测性以及产生速率对应用系统的效率和安全性具有重要价值。本文设计了一种基于超素数的组合式伪随机数序列生成算法，并利用FPGA进行了硬件实现和性能测试。论文对伪随机序列的产生原理、现有方法以及相关统计检验方法和标准进行了深入研究和讨论分析。所提出的组合式算法首先通过时钟计数器得到随机的初始种子和参数，，之后利用超素数发生器的特殊性质，得到出现概率相同的“0”、“1”序列，再利用扰乱函数对“0”、“1”序列进行扰乱重新排序，最后使用SHA_1安全散列算法完成对数列的进一步发散，来增强序列的随机性。本算法引入了不确定性和高速变换性因素，利用数据的奇偶性得到不规律的“0”、“1”序列，降低了生成数据之间的相关性，通过适时地改变发生器的相关参数，提高了伪随机序列的周期。为了对所提出的伪随机数发生器的速度和统计特性进行评估，利用Verilog HDL在FPGA上完成了算法的硬件实现，生成序列通过了FIPS140-2和NIST SP800-22两个国际标准检测集的所有项目检验。实验结果表明所设计的伪随机数发生器占用资源较少，产生的序列具有良好的随机性,具有一定的实际应用价值。
[Abstract]:Pseudorandom number generators are widely used in the field of computer simulation and information security. The randomness, unpredictability and production rate of pseudorandom number sequences are of great value to the efficiency and security of application systems. In this paper, a combined pseudorandom sequence generation algorithm based on superprime number is designed, and the hardware implementation and performance test are carried out by using FPGA. In this paper, the generation principle of pseudorandom sequence, the existing methods, and the relevant statistical test methods and standards are discussed and analyzed. The combined algorithm first obtains random initial seeds and parameters by clock counter, and then obtains "0" and "1" sequences with the same probability by using the special properties of superprime number generator. Then the "0" and "1" sequences are scrambled and reordered by the perturbation function. Finally, the further divergence of the sequence is accomplished by using the SHA_1 secure hash algorithm to enhance the randomness of the sequence. In this algorithm, uncertainty and high speed transformation are introduced, and the irregular "0" and "1" sequences are obtained by using the parity of data. The correlation between generated data is reduced, and the relevant parameters of generator are changed at the right time. The period of pseudorandom sequence is increased. In order to evaluate the speed and statistical characteristics of the proposed pseudorandom number generator, the hardware implementation of the algorithm is accomplished on FPGA with Verilog HDL, and the generated sequence is verified by all items of the two international standard detection sets, FIPS140-2 and NIST SP800-22. The experimental results show that the designed pseudorandom number generator occupies less resources and has good randomness and practical application value.
【学位授予单位】：哈尔滨工程大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP346

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