通用多核网络处理平台输出调度技术研究

发布时间：2018-05-25 23:33

本文选题：服务质量 + 队列调度　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：随着微电子、微处理器技术的不断发展,通用多核CPU的并发处理性能飞速提升,基于通用多核处理器的网络处理平台成为了研究的热点并且得到了广泛的应用。以通用多核处理器与硬件加速引擎结合的方式构建网络处理平台,既可以依靠通用多核处理器保证系统灵活性,又可利用硬件加速引擎实现系统的高速处理转发。输出调度是实现网络服务质量保证的重要手段,其面向于保证报文输出延迟和丢包率以及网络带宽的优化分配。基于通用多核CPU与硬件加速引擎结合的通用多核网络处理平台中,输出调度通常由硬件加速引擎实现。然而,由于硬件加速引擎存储空间受限以及通用多核CPU与硬件加速引擎间通信开销,输出调度架构和机制的设计面临较大挑战,尤其在报文输出延迟以及丢包率方面。针对通用多核网络处理平台架构在输出调度方面的问题,本文提出了一种新型输出调度架构——IntelliSchedule,主要工作与创新点包括:1面向通用多核网络处理平台设计特点,提出了一种新型的输出调度架构——Intelli Schedule。该架构融合了基于分类与基于端口的队列调度特点,采用多级调度模式,具有良好的可扩展性和系统性能;此外,基于该架构的报文预取以及流量控制技术,可以有效降低报文输出延迟,并提供无丢包的服务质量保证。。2基于Intelli Schedule架构,提出了一种延迟敏感的报文预取技术De SPreFetch,利用调度延迟隐藏访存延迟,降低报文整体输出调度延迟;此外,提出了一种丢包敏感的流量控制技术Lo SControl,在调度器即将发生拥塞时,通过减少发送线程数,将报文缓存在系统内存,保证系统输出端报文的无损传输。理论分析表明,与传统机制对比,两种关键技术分别降低了系统延迟和丢包率。3基于CompassNP平台对Intelli Schedule架构进行了功能实现和验证。设计实现了一种可重用的IntelliSchedule输出调度IP核,可通过软件配置灵活支持RR、DRR、PQ等多种调度算法,并基于CompassNP平台对该IP核进行了性能分析。综上所述,本文提出了一种面向通用多核网络处理平台的输出调度架构IntelliSchedule,对于通用多核网络处理平台服务质量保证具有重要的理论意义和实践价值。
[Abstract]:With the continuous development of microelectronics and microprocessor technology, the concurrent processing performance of universal multi-core CPU has been rapidly improved. The network processing platform based on universal multi-core processor has become a hot spot and widely used. It is an important means to ensure the quality of the network service, and the output scheduling is an important means to guarantee the quality of the network service. It is oriented to ensuring the packet output delay and the packet loss rate and the network bandwidth optimization. Based on the universal multi-core CPU and hardware acceleration engine junction, the output scheduling is based on the hardware acceleration engine junction. In the common multi-core network processing platform, the output scheduling is usually implemented by hardware acceleration engine. However, due to the limited storage space of the hardware acceleration engine and the communication overhead between the universal multi-core CPU and the hardware acceleration engine, the design of the output scheduling architecture and mechanism is facing great challenges, especially in the packet output delay and the packet loss rate. In view of the problem of output scheduling in general multi-core network processing platform architecture, a new type of output scheduling architecture, IntelliSchedule, is proposed in this paper. The main work and innovation points include: 1 for the design characteristics of universal multi-core network processing platform, and a new type of output scheduling architecture, Intelli Schedule., is proposed. Combining the characteristics of queue scheduling based on classification and port based scheduling, multilevel scheduling model is adopted, which has good scalability and system performance. In addition, the message prefetching and traffic control technology based on the architecture can effectively reduce the delay of message output and provide a..2 based Intelli Schedule architecture without loss of packet. A delay sensitive message prefetching technique De SPreFetch, which uses scheduling delay to hide the memory delay, reduces the overall output scheduling delay of the message. In addition, a packet loss sensitive traffic control technology, Lo SControl, is proposed. When the scheduler is about to congestion, the message is cached in the system memory by reducing the number of sending threads, and the guarantee system is guaranteed. The theoretical analysis shows that, compared with the traditional mechanism, the two key technologies reduce the system delay and the packet loss rate respectively,.3 based on the CompassNP platform to implement and verify the Intelli Schedule architecture. A reusable IntelliSchedule output scheduling IP kernel is designed and implemented, which can be configured by software configuration. A variety of scheduling algorithms such as RR, DRR, PQ and other scheduling algorithms are flexibly supported, and the performance analysis of the IP kernel is carried out based on the CompassNP platform. To sum up, this paper presents an output scheduling architecture for universal multi-core network processing platform, which has important theoretical significance and Practice for the quality assurance of universal multi-core network processing platform. Value.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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