前导零预测逻辑的设计与应用

发布时间：2018-05-26 21:13

本文选题：前导零预测器 + 并行纠错　；参考：《西安电子科技大学》2016年硕士论文

【摘要】：一直以来,浮点运算能力对于微处理器性能的评估至关重要。随着微电子技术的不断发展,高性能的浮点乘加部件(Multiply-Add-Fused,MAF)和加法器在浮点运算单元的设计上,有着很高的地位。前导零预测器(Leading Zero Anticipation,LZA)并行于加法器工作,用于直接计算出浮点加法结果中首个1的位置,并通过前导零检测器(Leading Zeros Detector,LZD)得到前导零数目。其对IEEE-754算术标准中所规定的浮点运算的规格化操作阶段进行了优化,是高性能加法电路和乘加电路中的关键部分。前导零预测器从预测结果的精确度上大致可分为两种,一种是精确预测,一种是一位误差预测。本文对前导零预测的算法与电路实现进行研究,设计并实现两种不同结构的精确前导零预测器,并对三操作数前导零预测器进行电路实现。本文的主要工作如下:首先,本文对基本的前导零预测算法进行介绍,描述了经典的前导零预测器结构,实现了对加法结果中首1位置的预测。并结合乘加器结构,描述了前导零预测逻辑在传统乘加器中的实现与应用。但由于预测数位后序列码型的不同情况,会导致1位预测误差的产生,因此该预测器为非精确预测。然后,对精确前导零预测的算法进行研究,主要探讨了并行纠错和基于进位信号纠错两种前导零纠错算法。并行纠错算法在对预测出的首1位置序列进行检测的同时,通过编码树电路每两位检测得到出错码型,最终得到纠错信号,对规格化数目进行修正。基于进位信号纠错利用加法器中对应预测的结果中首个1位置的进位信号,对是否出现预测误差进行判断。同时,还描述了三操作数前导零预测算法。其次,本文实现了计算序列中前导零数目的前导零检测器,其主要应用于对首1位置预测序列的检测。并分别基于并行纠错前导零算法与进位纠错前导零算法,实现两种不同结构的精确前导零预测器电路。对于并行纠错前导零预测器结构,整个电路并行于加法器执行,减小了电路延迟,提升了电路性能。对于进位纠错的前导零预测器结构,利用加法器中的进位信号使整个电路逻辑简单,整体的电路面积较小。之后,根据三操作数前导零预测算法,完成三操作数前导零预测器的电路设计。最后,本文对三种结构进行对比,对各自的特点及适用情况进行分析。并通过VHDL硬件描述语言完成了上述三种结构的电路描述,对电路进行了功能仿真,保证其功能的正确性。同时对其进行了逻辑综合,检测其电路性能。
[Abstract]:The floating-point computing ability is very important to evaluate the performance of microprocessor. With the development of microelectronic technology, the high performance floating-point multiplying and adding parts (Multiply-Add-FusedMAF) and adder play a very important role in the design of floating-point operation unit. The leading Zero precursor (LZA) works in parallel with the adder, which is used to calculate the position of the first 1 in the floating-point addition directly, and to obtain the number of leading zeros by leading Zeros detector LZD. It optimizes the standard operation stage of floating-point operation in IEEE-754 arithmetic standard and is the key part of high performance additive circuit and multiplication circuit. Leading zero predictors can be roughly divided into two types from the accuracy of prediction results, one is accurate prediction, the other is one bit error prediction. In this paper, the algorithm and circuit implementation of leading zero prediction are studied, two kinds of accurate leading zero predictors with different structures are designed and implemented, and the three operands leading zero predictors are implemented by circuit. The main work of this paper is as follows: first, this paper introduces the basic leading zero prediction algorithm, describes the classical structure of the leading zero predictor, and realizes the prediction of the first position in the addition result. The realization and application of leading zero predictive logic in traditional multiplier adder are described. However, due to the difference in the code types of the predicted digital sequence, the one-bit prediction error will be generated, so the predictor is an inexact predictor. Then, the algorithm of accurate leading zero prediction is studied, and two kinds of leading zero error correction algorithms based on carry signal and parallel error correction are mainly discussed. The parallel error correction algorithm detects the first position sequence of the first position, and obtains the error pattern by every two bit detection in the coding tree circuit. Finally, the error correction signal is obtained, and the normalized number is corrected. Based on the error-correction of carry signal, using the carry signal of the first 1 position in the corresponding prediction result in the adder, the prediction error is judged. At the same time, a three-Operand leading zero prediction algorithm is also described. Secondly, a leading zero detector for calculating the number of leading zeros in the sequence is implemented, which is mainly applied to the detection of the first position prediction sequence. Based on the parallel error correction leading zero algorithm and carry error correction leading zero algorithm, two kinds of accurate leading zero predictor circuits with different structures are implemented. For the parallel error correction leading zero predictor structure, the whole circuit is executed in parallel with the adder, which reduces the circuit delay and improves the circuit performance. For the leading zero predictor structure of carry error correction, the carry signal in the adder makes the whole circuit logic simple, and the whole circuit area is small. Then, according to the three-Operand leading zero prediction algorithm, the circuit design of the three-Operand leading zero predictor is completed. Finally, this paper compares the three structures and analyzes their characteristics and application. The circuit description of the above three structures is completed by VHDL hardware description language, and the functional simulation of the circuit is carried out to ensure the correctness of its function. At the same time, the logic synthesis is carried out, and the circuit performance is tested.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP332.2

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