基于MPSoC的DDR3存储器接口设计

发布时间：2018-05-27 09:34

本文选题：MPSoC + DDR3SDRAM　；参考：《南京大学》2013年硕士论文

【摘要】：随着基于MPSoC技术的多核处理器硬件设计规模和复杂度不断增加,以及外设接口的要求越来越丰富,系统架构师必须解决高性能系统应用的一些复杂问题,包括体系结构、算法和功能范围。一般而言,这些应用中一个基本的问题是存储器,随着MPSoC计算系统数据带宽的增加,以及处理器处理能力的增强,对存储容量、数据带宽以及访问延时的要求也不断提高,MPSoC架构下的访存带宽和数据传输效率问题成为新的关键问题。论文首先详细介绍了作者所在课题组自主设计的一款层次化异构多核处理芯片的体系结构和功能。该芯片采用NoC通讯结构,处理器和各种IP核通过资源接口与网络通讯。为了保证数据处理单元和存储器间的高效数据交换,该多核处理芯片的外部存储器部件采用了最新一代DDR3SDRAM。DDR3SDRAM存储器能够在节省系统功耗、提高系统性能的同时实现最大化的吞吐量。论文从介绍该多核处理芯片的硬件架构及其特征入手,着重介绍DDR3存储器接口的设计及验证的过程。在DDR3存储器接口设计中,作者采用了Xilinx公司最新的MIG高速存储器接口方案。该方案允许用户在Virtex-6等器件中通过用户接口(user interface)快速建立FPGA内部控制逻辑到外部存储器的连接。作者又自主设计了DDR3存储器接口IP核的用户接口模块-DDR3NI,该模块主要作用是将来自NoC路由器网络中的PCC信号转换成DDR3存储器IP核用户接口的相关信号,以起到两种协议相互转换的作用。论文最后介绍了在进行软硬件协同验证时所设计的一套Flash烧写验证平台,并利用该Flash烧写验证平台对DDR3存储器控制器进行了板级实际验证。验证的结果说明本文所设计的DDR3存储器接口工作正常且具有访存高效率、高带宽等特点。
[Abstract]:With the increasing scale and complexity of multi-core processor hardware design based on MPSoC technology, and the increasing requirements of peripheral interfaces, system architects must solve some complex problems in high-performance system applications, including architecture. Algorithm and functional range. Generally speaking, one of the basic problems in these applications is memory. With the increase of data bandwidth of MPSoC computing system and the enhancement of processor processing power, the storage capacity, The requirements of data bandwidth and access delay are also becoming more and more important in MPSoC architecture. Firstly, the architecture and functions of a hierarchical heterogeneous multicore processing chip designed by our team are introduced in detail. The chip uses NoC communication structure, the processor and various IP cores communicate with the network through the resource interface. In order to ensure the efficient data exchange between the data processing unit and the memory, the external memory component of the multi-core processing chip uses the latest generation of DDR3SDRAM.DDR3SDRAM memory to save the power consumption of the system. The system performance is improved and the throughput is maximized. This paper introduces the hardware architecture and characteristics of the multi-core processing chip, and focuses on the design and verification of the DDR3 memory interface. In the design of DDR3 memory interface, the author adopts the latest MIG high-speed memory interface scheme of Xilinx Company. This scheme allows users to quickly establish the connection of FPGA internal control logic to external memory through user interface in devices such as Virtex-6. The author also designs the user interface module of DDR3 memory interface IP core-DDR3NI. the main function of the module is to convert the PCC signal from NoC router network to the related signal of DDR3 memory IP core user interface. In order to play the role of the two protocols to each other. Finally, this paper introduces a set of Flash burn verification platform which is designed for hardware and software co-verification, and makes use of the Flash burn verification platform to verify the DDR3 memory controller at the board level. The verification results show that the DDR3 memory interface designed in this paper works normally and has the characteristics of high memory access efficiency and high bandwidth.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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