基于LEON3处理器外部存储器控制器加固设计

发布时间：2018-05-30 17:07

本文选题：BCH码 + 汉明码　；参考：《哈尔滨工业大学》2012年硕士论文

【摘要】：SoC中的存储器在辐射环境中容易受到各种辐射效应的影响。其中总剂量效应和单粒子效应对存储器的影响最大。总剂量效应使存储器MOS管阈值电压漂移、漏电增大，从而导致其电路速度降低、功耗增加甚至失效。单粒子效应可能使存储器发生硬错误和软错误。随着集成电路工艺的不断进步，特征尺寸不断缩小，总剂量效应对存储器的影响在不断减小，而存储器由于单粒子效应发生翻转的概率却越来越高。因此，在设计抗辐射SoC时可以采用错误探测与纠正（EDAC）技术加固外部存储器控制器（EMC），提高外部存储器抗单粒子翻转能力。本文首先介绍线性分组码理论，研究其编解码电路实现方式，并采用修正汉明码（39,32）和BCH码设计错误探测和纠正电路。修正汉明码（39,32）能够纠正任意一位错误，并探测两位错误。采用该码设计的错误探测与纠正电路保护存储在PROM中的数据。而加固SRAM的错误探测与纠正电路采用BCH码。本文使用的BCH码为扩展码BCH（45,32），它能够纠正任意两位错误，并探测三位错误。由于编解码电路应用于外部存储器，需要并行译码，因此本文采用查表译码方式实现译码。在设计好编解码电路的基础上，本文研究了错误探测与纠正电路的实现。由于对PROM加固的错误探测与纠正电路结构简单易于实现，，本文重点设计对SRAM加固的错误探测与纠正电路。对SRAM加固的错误探测与纠正电路，支持8位、16位和32位数据读写操作。此外，它能够纠正数据中任意两位错误，并能将纠正后的数据重新写入存储器中避免软错误的积累。最后，使用Verilog语言实现具有错误探测与纠正功能的外部存储器控制器，并搭建基于LEON3处理器SoC验证平台对其进行了系统验证，结果表明设计的电路能够正常工作。
[Abstract]:Memory in SoC is vulnerable to various radiation effects in radiation environment. The total dose effect and single particle effect have the greatest effect on the memory. The total dose effect makes the threshold voltage drift and leakage increase in the memory MOS transistor, which leads to the decrease of the circuit speed, the increase of power consumption and even the failure of the circuit. Single particle effect may cause hard and soft errors in memory. With the development of integrated circuit technology, the characteristic size is shrinking and the total dose effect on the memory is decreasing. However, the probability of the memory turning over due to the single particle effect is higher and higher. Therefore, in the design of anti-radiation SoC, the technology of error detection and correction can be used to reinforce the external memory controller and improve the ability of external memory to resist single particle flipping. In this paper, the theory of linear block code is introduced, the realization of coding and decoding circuit is studied, and the error detection and correction circuit is designed by using modified Hanming code 39n32) and BCH code. Fixed hamming code 39 / 32) corrects any bit error and detects two-digit errors. The error detection and correction circuit designed by this code is used to protect the data stored in PROM. The BCH code is used in the error detection and correction circuit of the strengthened SRAM. The BCH code used in this paper is an extended code BCHF 45N 32, which can correct any two bit errors and detect three bit errors. Since the codec circuit is used in external memory, it needs parallel decoding, so this paper uses look-up table decoding method to realize decoding. Based on the design of codec circuit, the realization of error detection and correction circuit is studied in this paper. Because the structure of the error detection and correction circuit strengthened by PROM is simple and easy to realize, this paper focuses on the design of error detection and correction circuit for SRAM reinforcement. The error detection and correction circuit strengthened by SRAM supports 8 bit 16 bit and 32 bit data reading and writing operation. In addition, it can correct any two bit errors in the data and rewrite the corrected data to the memory to avoid the accumulation of soft errors. Finally, the external memory controller with the function of error detection and correction is realized by using Verilog language, and the system is verified based on the SoC verification platform of LEON3 processor. The results show that the designed circuit can work normally.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

【参考文献】