基于RRAM非易失平均7T1R静态随机存储器研究

发布时间：2018-05-30 21:46

本文选题：nvSRAM + 低功耗　；参考：《安徽大学》2017年硕士论文

【摘要】：随着半导体产业不断壮大,制造工艺飞速提升使得MOS管尺寸不断缩小,但不断缩小的尺寸导致SRAM对电路制造工艺的偏差要求更加的苛刻,对于工艺波动更加敏感,性能也越发不稳定。然而市场对于高速高性能低功耗的SRAM需求日益增加。为了满足低功耗的市场需求,降低电源电压技术已经被提出,然而降低电压将导致其静态噪声容限减小从而导致SRAM的稳定性进一步降低。并且随着SRAM单元数目的不断增加,SRAM在静态保持状态下的泄漏功耗仍然不容忽视。尤其是对于一些常关断的系统而言泄漏功耗远大于动态功耗时,减小泄漏功耗对于增加电池寿命至关重要。此外,对于传统SRAM在系统电源关断后,存储数据会随之消失,当再次上电时SRAM单元存储的信息为随机值,无法恢复掉电前存储的数据,这对于需要保存大量现场数据及各种系统参数的应用系统来说无疑是不允许的。虽然非挥发性存储器有掉电后保存数据的能力,但其速度慢无法替代SRAM高速高性能低功耗的优势。为了保留SRAM在芯片上的优势,许多芯片采用"双宏结构"(two-macro),该结构包含易失性与非易失性存储器,正常工作时与SRAM工作原理相同,在掉电时用非易失性存储器备份SRAM数据,再次上电时由非易失性存储器将SRAM掉电前的数据写回SRAM,在实现SRAM掉电信息存储同时保留SRAM高速高性能低功耗优势,然而这种方法采用逐字传递易失(volatile)与非易失性存储器(nonvolatile memories)之间的数据,掉电备份与上电恢复数据速度慢,过长的掉电与上电时间不但降低了速度同时可能引起数据出错。为了降低SRAM静态保持功耗完成SRAM掉电数据存储,本文基于阻变随机存取存储器(RRAM)提出几种非易失性静态随机存储器(nonvolatile SRAM)。通过仿真对比分析了几种方案的优缺点,首先是调节驱动管尺寸实现可预知SRAM上电状态,该方案由于增加了每个单元尺寸相对于传统8T2R结构面积减小不明显,且恢复率较低,随后又提出打断SRAM放电路径实现可预知恢复方案,该方案节省了大量芯片面积,写能力显著提高,但同样恢复率较低,为此最终提出了各方面性能显著提升的方案。该电阻非易失性存储单元由7个晶体管和一个阻变随机存取存储器构成,包含一个非易失存储器(1T1R)和一个标准6管SRAM单元,而在nvSRAM每一列外加一个NMOS管构成本文提出的非易失平均7T1RnvSRAM(NVA-7T1R)。与现有几种nvSRAM对比本文提出的方案具有面积小,速度快,功耗低,读写能力强等优势。每列增加的下拉尾管极大的提升了单元写能力,与传统SRAM相比写能力提升近1倍。在数据恢复阶段由于打破了 SRAM耦合反相器的锁存,上电恢复SRAM数据时恢复速度为以往7T1R结构的2.5倍,单元直流功耗减小了 63%。
[Abstract]:With the continuous expansion of semiconductor industry, the rapid improvement of manufacturing process makes the size of MOS tube shrink, but the shrinking size of SRAM leads to more stringent requirements for the deviation of circuit manufacturing process, and more sensitive to process fluctuations. Performance is also increasingly unstable. However, the market for high-speed and high-performance low-power SRAM demand is increasing. In order to meet the market demand of low power consumption, the technology of reducing power supply voltage has been proposed. However, the reduction of voltage will reduce the static noise tolerance of SRAM and further reduce the stability of SRAM. And with the increasing of the number of SRAM cells, the leakage power consumption can not be ignored in the static state. Especially for some systems where the leakage power is much larger than the dynamic power consumption, it is very important to reduce the leakage power to increase the battery life. In addition, for the traditional SRAM, the stored data will disappear after the system power off, and the information stored in the SRAM unit will be random when the power is switched on again, so the data stored before the power down cannot be recovered. This is no doubt not allowed for applications that need to preserve large amounts of field data and various system parameters. Although non-volatile memory has the ability to save data after power down, its slow speed can not replace the advantages of SRAM high speed, high performance and low power consumption. In order to preserve the advantage of SRAM on chip, many chips adopt "two-macro structure" two-macro structure, which contains volatile and non-volatile memory, and works in the same way as SRAM, and uses non-volatile memory to back up SRAM data when power is down. When power on again, the data before SRAM power down is written back to SRAM by non-volatile memory, so that the storage of SRAM power down information is realized and the advantages of high speed, high performance and low power consumption of SRAM are preserved. However, this method adopts verbatim transmission of data between volatile memory and nonvolatile memory. The speed of power down backup and power on recovery data is slow, and too long power off and power on time not only reduces the speed but also may cause data error. In order to reduce the power consumption of SRAM to complete SRAM power-down data storage, this paper presents several nonvolatile random access memory (RRAM) based on resistive random access memory (RRAM). The advantages and disadvantages of several schemes are compared and analyzed by simulation. Firstly, the size of the drive tube is adjusted to realize the predictable power state of SRAM. Because of increasing the size of each unit, the reduction of the area of each unit compared with the traditional 8T2R structure is not obvious, and the recovery rate of the scheme is lower than that of the traditional 8T2R structure. Then a predictable recovery scheme by interrupting the discharge path of SRAM is proposed, which saves a lot of chip area and improves the write-ability significantly, but the recovery rate is also low. Finally, a scheme to improve the performance of all aspects is put forward. The resistive nonvolatile memory cell consists of seven transistors and a resistive random access memory, including a non-volatile memory 1T1R) and a standard 6-transistor SRAM cell. The nonvolatile average 7T1RnvSRAMN NVA-7T1RN is constructed by adding a NMOS tube to each column of nvSRAM. Compared with the existing nvSRAM, the proposed scheme has the advantages of small area, high speed, low power consumption and strong reading and writing ability. The addition of a drop-down tail tube in each column greatly improves the unit writing ability, nearly twice as much as the traditional SRAM. In the stage of data recovery, because of breaking the latch of the SRAM coupling inverter, the recovery speed of the SRAM data is 2.5 times that of the previous 7T1R structure, and the DC power consumption of the unit is reduced by 63 times.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333

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