基于增量编译的DSP内核IP的FPGA验证

发布时间：2018-05-31 14:27

本文选题：增量编译 + IP核　；参考：《西安电子科技大学》2012年硕士论文

【摘要】：FPGA原型验证的出现极大地提高了芯片验证的效率。使得设计人员能够在短时间内测试大量的程序，及早的发现设计中的错误。但同时这种大规模芯片的验证使得软件编译时间越来越长，即使小的改动，也要连同没有修改的部分一起重新编译，浪费了时间，降低了验证效率。本文在对XXX DSP内核IP验证的过程中，引入了增量式设计，将设计按照不同功能、关键时序路径等进行了设计分区，每次修改设计后，再次编译时，，软件会根据设计人员指定的分区网表类型，继承上一次编译的结果，只重新编译修改过的设计分区，极大地缩短了再次编译的时间，提高了FPGA验证的效率。本文具体工作如下：首先，通过研究增量编译的原理和设计方法，确定了通过Quartus II软件导出IP的方法以及使用IP的方法。其次，完成了ASIC设计到FPGA设计的代码转换工作，并通过功能验证的方法，保证了代码转换在行为级的正确性。接着，在成功导出DSP内核IP的基础上，采用增量式设计基于LMB总线搭建了IP验证环境，包括时钟模块、IP模块以及外部指令存储体模块。其中外部指令存储体模块又包含了从设备接口逻辑和存储体逻辑。从设备接口逻辑除了Split传输外，支持LMB总线的所有传输类型，如字节传输、半字传输、字传输、双字传输、读改写以及2、4、8节拍块传输。存储体逻辑实际上是一个ROM，宽度64bits，深度2048，是使用可综合的RTL编写的。最后，采用应用程序测试的方法，在XXX型高性能DSP IP FPGA性能评估系统硬件平台上，验证了XXX DSP内核IP的功能，并在验证过程中充分展现了增量编译的优势，提高了FPGA的验证效率。
[Abstract]:The appearance of FPGA prototype verification greatly improves the efficiency of chip verification. Allows designers to test a large number of programs in a short period of time, early detection of design errors. But at the same time, the verification of this kind of large-scale chip makes the software compile time longer and longer, even if the small changes, but also along with the unmodified part to recompile with the waste of time, reduce the efficiency of verification. In the process of IP verification of XXX DSP kernel, the incremental design is introduced in this paper. The design is partitioned according to different functions, critical timing paths and so on. After each modification of the design, the design is compiled again. According to the type of partition network table specified by the designer, the software inherits the result of the previous compilation and recompiles only the modified design partition, which greatly shortens the time of recompiling and improves the efficiency of FPGA verification. The specific work of this paper is as follows: Firstly, by studying the principle and design method of incremental compilation, the method of exporting IP through Quartus II software and the method of using IP are determined. Secondly, the code conversion from ASIC design to FPGA design is completed, and the correctness of code conversion at the behavior level is ensured by the method of function verification. Then, on the basis of successfully exporting DSP kernel IP, the IP verification environment based on LMB bus is designed incrementally, including clock module IP module and external instruction storage module. The external instruction storage module includes slave device interface logic and storage logic. The slave interface logic supports all types of transmission of the LMB bus except for Split transmission, such as byte transmission, half word transmission, double word transmission, read rewriting, and 2 / 4 / 8 beat block transmission. The storage logic is actually a mm, 64 bits wide, and 2048 depth, written in an integrated RTL. Finally, using the method of application program test, the function of XXX DSP kernel IP is verified on the hardware platform of XXX high-performance DSP IP FPGA performance evaluation system, and the advantage of incremental compilation is fully demonstrated in the verification process. The efficiency of FPGA verification is improved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.11;TN791

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