一种DSP处理平台的低功耗设计与实现

发布时间：2018-06-05 04:23

本文选题：低功耗设计 + 动态功耗管理　；参考：《中国舰船研究院》2013年硕士论文

【摘要】：随着电子技术的发展，嵌入式数字系统的处理能力得到了飞速的提升。但是在性能大幅提升的同时，系统的功耗也在急剧上升。过高的功耗不仅增大了系统的设计难度，并且对系统的稳定性以及可靠性产生了严重的影响。因此，功耗以及能耗问题越来越受到重视，高性能系统的功耗管理及低功耗设计技术也成为当前研究的热点。在实际运行中，系统在相当一部分的运行时间内处于空转或低负荷状态，这些时间段内系统所额外消耗的能量可以通过低功耗设计措施加以避免。低功耗设计的主要切入点即根据系统运行的实际负载，在保证按要求完成处理任务的前提下通过合理调低系统的相关性能以实现系统的低功耗运行。为了达到这一目标，需要在系统中实现可靠的低性能运行机制，对系统的各个部件进行有效监控并采用合理的策略对系统功耗加以管理。本文首先对高性能电子系统低功耗设计技术的现状进行了介绍，对以CMOS为基本单元的集成电路的功耗特性进行分析；结合现有的低功耗设计技术，，确定了功耗优化设计的主体思路：即在保证性能的前提下降低系统空闲时段功耗以及系统运行态功耗。接下来，在以TMS320C6678为核心的数字信号处理系统上，根据提出的低功耗设计思路，在芯片应用层面通过频率调节、功能分区以及工作模式控制的方式优化芯片的功耗；在处理平台上通过加入低速通信链路以及节点上下电管理模块等机制实现对处理板的功耗控制；并在单节点处理板上设计并实现了一个基于超时策略的功耗管理软件。最后对功耗优化方案进行了验证与测试，以分别测量系统电压、电流的方案设计并实现一个功耗测量模块，利用该模块对本文提出的功耗优化机制进行逐一测试。测试的结果表明，通过合理应用本文提出的功耗优化机制，系统的功耗得到了较为明显的改善。
[Abstract]:With the development of electronic technology, the processing ability of embedded digital system has been improved rapidly. But at the same time, the power consumption of the system is also rising sharply. Excessive power consumption not only increases the design difficulty of the system, but also has a serious impact on the stability and reliability of the system. Therefore, more and more attention has been paid to the problem of power consumption and energy consumption. The power management and low power design technology of high performance systems have become the focus of current research. In actual operation, the system is in idle or low load state for a considerable part of the running time, and the extra energy consumed by the system can be avoided by low-power design measures in these time periods. According to the actual load of the system, the main breakthrough point of low power design is to realize the low power operation of the system by reasonably reducing the correlation of the system under the premise of completing the processing task according to the requirement. In order to achieve this goal, it is necessary to realize reliable low performance operation mechanism in the system, monitor each component of the system effectively and adopt reasonable strategy to manage the power consumption of the system. In this paper, the current situation of low power design technology for high performance electronic systems is introduced, and the power characteristics of integrated circuits based on CMOS are analyzed. The main idea of power optimization design is to reduce the system idle time power and the system running state power under the premise of ensuring the performance. Then, in the digital signal processing system with TMS320C6678 as the core, according to the low power design idea proposed, the chip power consumption is optimized by frequency regulation, function partition and working mode control at the chip application level. The power consumption control of the processing board is realized by adding the low-speed communication link and the upper and lower power management module of the node on the processing platform, and a power management software based on the time-out policy is designed and implemented on the single-node processing board. Finally, the power optimization scheme is verified and tested to measure the voltage and current of the system, and a power measurement module is designed and implemented. The power optimization mechanism proposed in this paper is tested one by this module. The test results show that the power consumption of the system is improved obviously by applying the power optimization mechanism proposed in this paper.
【学位授予单位】：中国舰船研究院
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP368.1

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