基于动态存储的2Gbps数据流产生技术研究

发布时间：2018-06-05 07:44

本文选题：数据发生器 + 动态存储器　；参考：《电子科技大学》2012年硕士论文

【摘要】：数据发生器作为现代数据域测试中的通用数字信号源,可以产生大数据量、复杂多样的高速数字激励信号。随着现代科技水平的快速发展,待测设备的工作速度不断提高以及系统功能更加复杂化,相应的对数据发生器的数据输出速率和数据存储深度提出了更高要求,因此需要高速大容量存储器件作为图形数据存储器。随着存储器件的不断发展,动态存储器的出现极大的推动了高速数据流产生技术的研发。本论文首先介绍了动态存储器高速传输数据的工作原理,对其读写数据过程进行了深入研究,并通过分析数据发生器功能和指标要求,提出采用动态存储器作为图形数据存储器,以及采用异步FIFO对动态存储器输出数据进行缓存以达到数据无缝输出的要求,确定了基于动态存储的高速数据流产生系统总体设计方案。然后根据高速数据流产生系统的数据输出特点再结合动态存储器的读写数据过程,设计了基于动态存储的数据产生控制电路,以及具有正确读写动态存储器和无缝输出图形数据功能的DDR2存储模块,最终实现了2Gbps数据流输出和单通道256Mbits存储深度的双通道高速数据流产生系统。完成高速数据流产生系统与上位机控制系统(以Arm为控制核心)之间的接口模块设计,使上位机与数据流产生板能够进行数据信号通信,最终实现了在多种触发方式和运行模式下的高速数据流输出。
[Abstract]:As a universal digital signal source in modern data domain testing, data generator can generate large amount of data and complex high-speed digital excitation signal. With the rapid development of modern science and technology, the working speed of the equipment to be tested has been improved and the system function has become more complicated. Accordingly, the data output rate and the data storage depth of the data generator are required to be higher. Therefore, high speed and large capacity memory devices are needed as graphics data memory. With the continuous development of memory devices, the emergence of dynamic memory greatly promotes the development of high-speed data stream generation technology. In this paper, the principle of high speed data transmission in dynamic memory is introduced, and the process of reading and writing data is deeply studied, and the function and index requirement of data generator are analyzed. Dynamic memory is used as graphic data memory, and asynchronous FIFO is used to cache the output data of dynamic memory to achieve seamless data output. The overall design scheme of high speed data stream generation system based on dynamic storage is determined. Then according to the data output characteristics of high-speed data stream generation system and combined with the process of reading and writing data in dynamic memory, a data generation control circuit based on dynamic storage is designed. And the DDR2 storage module, which can read and write dynamic memory correctly and output graph data seamlessly, realizes the 2Gbps data stream output and single-channel 256Mbits storage depth two-channel high-speed data stream generation system. The design of the interface module between the high speed data stream generation system and the host computer control system (Arm as the control core) enables the data signal communication between the upper computer and the data stream generator board. Finally, the output of high-speed data stream in various trigger modes and running modes is realized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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