一款DSP硬核中加法器的全定制设计

发布时间：2018-06-05 19:57

本文选题：DSP + 全定制　；参考：《西安电子科技大学》2012年硕士论文

【摘要】：加法器是高性能微控制器、数字信号处理器非常重要的运算部件。高性能的加法器除了用于数学运算外，，还在加密、图像、语音等信号处理领域起着着非常重要的作用。加法器性能的优劣直接影响着整个系统的速度，对芯片的工作主频有很大的影响。因此，设计并优化加法器的结构将提高整个系统的速度、降低面积和功耗等。本文对加法器的理论进行了较为深入的研究，在此基础上实现了一个用于一款FPGA中DSP硬核的3输入48位加法/减法器的专用模块。结构方面，对三组48位的输入采用3:2压缩并与输入进位和加减控制信号组合使逻辑运算简化成两组48位数；48位加法器的设计通过比较分析采用了基于选择进位的混合树型的结构，该结构通过计算阶数为4的组进位输出来选择输出正确的结果。底层逻辑多采用CPL电路来实现具体电路。设计完成后，使用NC_Verilog，Nanosim分别对该专用模块进行了功能仿真和验证，验证结果表明该模块能够达到预期设计目标。
[Abstract]:Adder is a high performance microcontroller, digital signal processor is a very important computing unit. The high performance adder plays a very important role in the fields of encryption, image, speech and other signal processing. The performance of the adder directly affects the speed of the whole system and the main frequency of the chip. Therefore, the design and optimization of the adder structure will improve the speed of the whole system, reduce the area and power consumption. In this paper, the theory of adder is deeply studied, and a special module of 3-input 48-bit adder / subtractor for DSP hard core in FPGA is implemented. Structurally, Three groups of 48-bit input are compressed by 3:2 and combined with input carry and add and subtraction control signal. The logic operation is simplified into two groups of 48-bit number 48-bit adder. Through comparison and analysis, a hybrid tree structure based on selective carry is adopted. The structure selects the correct output by calculating the group carry output of order 4. The bottom logic uses CPL circuit to realize the concrete circuit. After the design is finished, the functional simulation and verification of the special module are carried out using NCCCVerilogan Nanosim, respectively. The results show that the module can reach the expected design goal.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.21;TP368.12

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