基于Petri网的ASIP体系结构研究

发布时间：2018-06-06 22:38

本文选题：专用指令集处理器 + MIPS　；参考：《武汉纺织大学》2012年硕士论文

【摘要】：ASIP（专用指令集处理器），它是一种具有可定制特性的处理器，应用在特定的领域，可为某些特定的应用进行专门的设计，能够很好的解决一些在嵌入式系统设计中遇到的问题，随着科技的进步，它在嵌入式领世界用得更多了。 RISC技术在是世纪八十年代兴起，是一类新的设计处理器的技术，其中CISC和RISC技术属于目前主流的设计技术，因为RISC技术指令集简单、译码容易，得到了更多的应用，流水线的设计是其中一个很重要的部分。流水线结构的使用将指令执行的速率提升了很多，MIPS属于RISC中的一个典型的版本，在MIPS结构的CPU上流水线技术得到了很好的应用。本文详细的介绍了MIPS架构，通过对MIPS处理器的研究，在Quartus软件上进行了寄存器堆、算数逻辑单元(ALU)、译码器等的设计，并且设计了MIPS处理器五级流水线，取指令（IF）、译码（ID）、执行（EXE）、访问寄存器（MEM）、寄存器写回（WB）这五个流水线模块，对设计好的处理器进行了综合和仿真，结果证明这个处理器设计是正确的。 Petri网模型的并发性等特点，使得它在流水线结构建模上拥有很大优越性。通过对Petri网模型的研究，得出Petri网模型能够使用HDL（硬件描述语言）来描述，在现有的软件平台Quartus上对Petri网模型的进行了编译和综合仿真，并在Quartus中生成了Petri网元素的元件库。在基于前面设计的MIPS处理器五级流水线的基础上进行了建模，，证明用Petri网进行ASIP流水线的描述是可行的。
[Abstract]:ASIP (Special instruction set processor) is a kind of processor with customizable characteristics, which can be used in specific fields and can be specially designed for certain applications, which can solve some problems encountered in the design of embedded system. With the progress of science and technology, it is more and more used in the embedded world. RISC technology rose in the 1980s, is a new kind of design processor technology, CISC and RISC technology is the mainstream design technology, Because the instruction set of RISC technology is simple and the decoding is easy, the pipeline design is a very important part. The use of pipelined architecture increases the speed of instruction execution many MIPS belong to a typical version of RISC. Pipelining technology has been well applied in MIPS CPU. This paper introduces the MIPS architecture in detail. Through the research of MIPS processor, the register file, arithmetic logic unit (ALU), decoder and so on are designed on Quartus software, and the five-stage pipeline of MIPS processor is designed. In this paper, five pipeline modules are taken, such as IFI / IFT, decoding / IDN, executing EXEN, visiting register / MEMN, and register writing back to WB), and the designed processor is synthesized and simulated. The result shows that the processor design is correct and the concurrency of Petri net model is correct, and so on, and the simulation results show that the design of the processor is correct, and the concurrency of the Petri net model is also proved to be correct. It has great superiority in pipeline structure modeling. Through the research of Petri net model, it is concluded that the Petri net model can be described by using HDL (hardware description language), and the Petri net model is compiled and synthesized on the existing software platform Quartus, and the element library of Petri net element is generated in Quartus. Based on the five-stage pipeline of MIPS processor designed earlier, it is proved that it is feasible to use Petri net to describe ASIP pipeline.
【学位授予单位】：武汉纺织大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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