双通道SDRAM存储控制模块的设计与实现

发布时间：2018-06-07 00:15

本文选题：射频芯片测试 + 多通道数据存储　；参考：《东南大学》2015年硕士论文

【摘要】：随着多模多频射频芯片(RFIC)的广泛应用,多模多频RFIC芯片的测试日益成为人们关注的焦点。然而,在进行多模多频RFIC多路接收通道并行测试时离不开多通道、高速、连续的存储控制模块。因此,基于FPGA的RFIC自动测试设计一款双通道SDRAM数据存储控制模块具有重要意义。本文主要目的是设计一个能够自适应模数转换器(ADC)采样速率在26MHz-61.44MHz范围内变化的双通道SDRAM数据存储控制模块,实现对RFIC芯片输出的最高数据流速率为61.44MHz×28b的两路连续并行基带数据的正确存储,以便后续的数据处理和分析。首先,本文采用了基于异步FIFO的缓存方案解决了存储过程中面临的两个主要问题：SDRAM因刷新、换行等操作造成的非数据传输无法满足连续数据流实时存储的问题和数据流速率与存储速率相异步的问题。其次,本文着重对异步FIFO缓存进行了两个方面的优化和改进：第一,为了解决两路数据对SDRAM存储器共享的问题,本论文设计了一个基于加权轮询(WRR)调度算法的仲裁模块以保证双通道数据带宽需求；第二,为节约资源,在保证数据有效带宽利用率的前提下,降低了缓存中异步FIFO的深度。最后,本文搭建了一个由RFIC自动测试的FPGA开发板、AD采集板、Agilent 16902B逻辑分析仪、Agilent E3631A直流稳压源、Agilent 33500B波形发生器、E4438C矢量信号发生器和PC机构成的验证平台对研究成果进行FPGA验证。结果表明该存储控制方案在SDRAM芯片MT48LC32M16A2工作电压为3.3V,工作频率为133MHz,异步FIFO深度只有16个字的情况下,能实现采样率为64.285713MHz,位宽为32位的两路连续并行数据流的存储,即数据传输有效带宽利用率能达到96.67%。
[Abstract]:With the wide application of multi-mode multi-frequency RF chip, the test of multi-mode multi-frequency RFIC chip has become the focus of attention. However, parallel testing of multimode and multi-frequency RFIC reception channels can not be separated from multi-channel, high-speed, continuous memory control module. Therefore, it is of great significance to design a dual channel SDRAM data storage control module based on RFIC automatic test based on FPGA. The main purpose of this paper is to design a dual-channel SDRAM data storage control module which can change the sampling rate in the range of 26MHz-61.44MHz. To realize the correct storage of two consecutive parallel baseband data with the highest data flow rate of 61.44MHz 脳 28b output from the RFIC chip for subsequent data processing and analysis. First of all, this paper uses the cache scheme based on asynchronous FIFO to solve the two main problems in the stored procedure: SDRAM refresh. The non-data transmission caused by newline operation can not satisfy the problem of continuous data stream real-time storage and the problem of asynchronous data stream rate and storage rate. Secondly, this paper focuses on the optimization and improvement of asynchronous FIFO cache in two aspects: first, in order to solve the problem of SDRAM memory sharing between two channels of data, In this paper, we design an arbitration module based on weighted polling WRR scheduling algorithm to ensure two-channel data bandwidth requirements. Secondly, in order to save resources, we reduce the depth of asynchronous FIFO in cache on the premise of ensuring the effective bandwidth utilization of data. Finally, a verification platform composed of FPGA development board and AD acquisition board based on RFIC automatic test is set up to verify the research results by FPGA, which is made up of Agilent E3631A DC voltage stabilized source generator and E4438C vector signal generator. The results show that the memory control scheme can realize the storage of two continuous parallel data streams with a sampling rate of 64.285713MHz and a bit width of 32 bits when the operating voltage of MT48LC32M16A2 is 3.3 V, the working frequency is 133MHz, and the depth of asynchronous FIFO is only 16 words. That is, the effective bandwidth utilization rate of data transmission can reach 96.67.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP333

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