ARM并行阵列机中的路由器设计

发布时间：2018-06-07 22:32

本文选题：路由器 + 缓存机制　；参考：《微电子学与计算机》2017年02期

【摘要】：针对ARM并行阵列机结构,提出了与之相适应的通信结构,采用4个路由器完成16个处理器内核之间的通信,有效地节约了面积.该路由器采用基于数据包交换的片上网络通信方式,内部运用缓存机制、经典的XY路由算法和专用的仲裁策略再加入数据多播,且处理器选用低功耗、高性能的ARM内核,通过采用以上机制能够有效降低数据传播延迟和功耗.实验结果表明采用该方案设计的路由器时钟频率最高可达406.009 MHz,能够满足该ARM阵列机对于通信速率的要求.
[Abstract]:In view of the structure of ARM parallel array machine, a communication structure adapted to it is proposed. The communication between 16 processor cores is completed by 4 routers. The area is saved effectively. The router uses a packet based network communication mode based on packet switching, the internal application of caching machine, the classic XY routing algorithm and the special arbitration strategy. Data multicast is added, and the processor selects low power and high performance ARM kernel. By using the above mechanism, the data propagation delay and power consumption can be effectively reduced. The experimental results show that the clock frequency of the router designed with this scheme can reach up to 406.009 MHz, which can satisfy the requirement of the communication rate of the ARM array machine.
【作者单位】：西安邮电大学电子工程学院;西安邮电大学计算机学院;
【分类号】：TP332

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