基于FPGA和SATA3.0接口的高速大容量存储系统的设计与实现

发布时间：2018-06-10 16:04

本文选题：SATA + 3.0　；参考：《南京邮电大学》2017年硕士论文

【摘要】：信息技术的发展离不开存储技术的助力,因此对存储系统的研究具有相当的应用价值。本次课题旨在在FPGA平台上利用SATA3.0接口设计实现一个高速大容量存储系统,主要的工作是研究并实现SATA3.0读写控制器的关键技术。SATA是一种高速串行总线协议,因其采用两对差分线分别进行串行发送和接收,能够有效地避免总线干扰,故而取代PATA成为新一代的传输接口。SATA凭借其传输速率高、纠错能力强、支持热插拔等特点而得到了广泛的应用,SATA3.0接口的最高传输速率更是达到了600MB/s,因此适用于高速大容量存储系统的设计。本文首先介绍了SATA3.0协议的四层结构:物理层、链路层、传输层和应用层,并对每一层的功能以及主要的功能模块进行介绍。然后利用Quartus II设计平台并采用了自底向上的模块化设计方法,分别设计实现了SATA3.0协议物理层收发器的配置,链路层扰码模块和CRC校验模块的设计以及传输层封装模块的设计。在本文的最后,分别给出了软件仿真和板级测试的结果。首先利用Modelsim仿真软件分别对设计的各个模块进行功能性的仿真验证,仿真结果表明各个模块都能实现各自的逻辑功能。最后对整个系统进行的读写测试表明系统能够正确地进行读写并且性能基本满足SATA3.0协议要求。
[Abstract]:The development of information technology can not do without the help of storage technology, so the research of storage system has considerable application value. The purpose of this project is to design and implement a high speed and large capacity storage system on FPGA platform using SATA3.0 interface. The main work is to study and implement the key technology of SATA3.0 read and write controller. SATA is a high speed serial bus protocol. Because two pairs of differential lines are used for serial transmission and reception, which can effectively avoid bus interference, PATA is replaced as a new generation of transmission interface. SATA has high transmission rate and strong error correction ability. It has been widely used in the design of high speed and large capacity storage system because of its characteristics such as hot swapping and so on. The maximum transmission rate of SATA3.0 interface is 600MB / s, so it is suitable for the design of high speed and large capacity storage system. This paper first introduces the four layers of SATA3.0: physical layer, link layer, transport layer and application layer, and introduces the functions of each layer and the main function modules. Then, using Quartus II design platform and adopting bottom-up modularization design method, the configuration of physical layer transceiver of SATA3.0 protocol, the design of link layer scrambling code module and CRC check module and the design of transmission layer encapsulation module are designed respectively. At the end of this paper, the results of software simulation and board-level test are given respectively. Firstly, the function of each module is verified by Modelsim simulation software. The simulation results show that each module can realize its own logic function. Finally, the reading and writing test of the whole system shows that the system can read and write correctly and the performance basically meets the requirements of SATA 3.0 protocol.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333

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