片上系统DCR、OPB总线及相关模块的设计与验证

发布时间：2018-06-12 00:34

本文选题：片上系统 + 片上总线　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：由于半导体工艺技术的不断发展，IC设计者能够将复杂的功能集成到单硅片上。正是在集成电路(IC)向集成系统(IS)转变的潮流下，片上系统（SoC）应运而生。片上系统的产生使得基于IP重用的设计方法开始出现，这对整合众多IP有着重大意义，所以片上总线及其接口的效率决定了SoC的效率。论文主要以DCR和OPB总线为基础设计了多个可重用模块，包括八路PWM模块、四路频率采集器模块和三路光栅编码器模块。分析了它们的设计思路以及要达到的目标。针对每一个模块编写了对应的测试激励，使用直接测试方法，给各个模块以特定的输入，查看每个模块的输出结果。模块设计完成后，把每个模块与对应的总线相连时，但数据的输入有时不会按照所预期的被采集到，通过加入同步模块可以避免这种情况的发生。本文设计的三个模块以重用于类似的总线时序要求中。在其他芯片设计中如果用到这三个模块时，直接使用，，省去了大量的设计的时间，这正是本论文的设计工作的意义。
[Abstract]:With the continuous development of semiconductor technology, IC designers can integrate complex functions onto monolithic wafers. It is under the trend that integrated circuit (IC) is transformed into integrated system (ISS) that the system on chip (SoC) emerges as the times require. The emergence of on-chip systems has led to the emergence of design methods based on IP reuse, which is of great significance to the integration of many IP. Therefore, the efficiency of SoC is determined by the efficiency of on-chip bus and its interface. Based on DCR and OPB bus, several reusable modules are designed in this paper, including eight PWM module, four frequency collector module and three grating encoder module. Analysis of their design ideas and objectives to be achieved. For each module to write the corresponding test incentives, using the direct test method, to each module with specific input, to view the output of each module. After the module design, each module is connected to the corresponding bus, However, the input of data is not always collected as expected, which can be avoided by adding synchronization module. The three modules designed in this paper are reused in similar bus timing requirements. If these three modules are used directly in other chip designs, a lot of design time is saved, which is the significance of the design work in this paper.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN47

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