嵌入式平台中的PCI Express总线技术研究

发布时间：2018-06-13 09:41

  本文选题：PCI + Express链路　； 参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着信息技术的发展,数字信息资源的体积有了较大的膨胀,数字设备之间交换数据量越来越大。日益增长的数据量对高速数据传输接口的需求变得更加迫切。为满足这个需求,PCI Express总线技术应运而生,并被广泛应用于个人电脑中。随着嵌入式系统性能的提升,PCI Express总线技术在嵌入式领域也得到越来越广泛的应用。嵌入式平台的主要核心基本上是处理器和可编程逻辑器件(FPGA)两部分,而且越来越多的处理器和FPGA支持高速PCI Express总线接口。基于此,本文研究了PCI Express技术在基于FPGA和处理器平台中的高速数据传输应用,设计并实现了一种FPGA与PowerPC处理器通信方案,并且在该方案的基础上,进一步对PCI Express技术在多个PowerPC处理器通信中的应用进行了探索和实践,最终实现了多个嵌入式PowerPC处理器的PCIe通信方案。在FPGA与处理器的PCIe通信系统中,由嵌入式PowerPC处理器作为根复合体(RC)设备,FPGA作为EP(端点)设备,二者直接建立PCIe链路进行通信;而在多个嵌入式PowerPC处理器的PCIe通信系统中,由一颗PowerPC处理器作为RC设备,其它PowerPC处理器作为EP设备,并通过交换芯片对PCIe链路进行扩展,建立起一对多的PCIe链路。所介绍的两种嵌入式平台的软件设计均基于嵌入式Linux系统,Linux应用程序通过PCIe设备驱动程序实现了对PCIe链路的初始化和控制。本文在两种嵌入式平台上所完成的工作有:1.在FPGA与嵌入式PowerPC处理器的PCIe通信系统中,基于Xilinx公司的Virtex6系列FPGA的片内PCIe核实现了PCIe EP设备,与作为RC设备的MPC8377处理器建立PCIe链路。运行在MPC8377上的嵌入式Linux应用程序配合EP驱动程序访问FPGA,实现FPGA和PowerPC处理器的通信。2.在多个嵌入式Power PC处理器的PCIe通信系统中,实现了多颗MPC8377的PCIe通信。其中一颗处理器在switch上游作为RC设备,而其它处理器在switch下游作为EP设备。运行在RC端的嵌入式Linux应用程序配合EP驱动程序,实现了与EP处理器的通信。论文分别给出了两种嵌入式平台运行测试的结果,证明其完全满足设计要求。
[Abstract]:With the development of information technology, the volume of digital information resources has expanded greatly. The demand of high-speed data transmission interface becomes more and more urgent due to the increasing amount of data. In order to meet this requirement, PCI Express bus technology emerged as the times require, and has been widely used in personal computers. With the improvement of embedded system performance, PCI Express bus technology has been more and more widely used in embedded field. The main core of embedded platform is basically processor and programmable logic device (FPGA), and more processors and FPGA support high-speed PCI Express bus interface. Based on this, this paper studies the application of PCI Express technology in high speed data transmission based on FPGA and processor platform, and designs and implements a communication scheme between FPGA and PowerPC processor. Furthermore, the application of PCI Express technology in multiple PowerPC processors is explored and put into practice. Finally, the PCIe communication scheme of multiple embedded PowerPC processors is implemented. In the PCIe communication system between FPGA and processor, the embedded PowerPC processor is used as the root complex device and FPGA is used as the EPIe device, and the PCIe link is directly established for communication between the two devices, while in the PCIe communication system of multiple embedded PowerPC processors, Using one PowerPC processor as RC device and other PowerPC processors as EP devices, a one-to-many PCIe link is established by extending the PCIe link through switching chips. The software design of the two embedded platforms is based on the embedded Linux system and Linux application program, which realizes the initialization and control of the PCIe link through the PCIe device driver. The work of this paper on two embedded platforms is: 1. 1. In the PCIe communication system between FPGA and embedded PowerPC processor, the PCIe core based on Xilinx's Virtex6 series FPGA implements the PCIe EP device, and establishes the PCIe link with the MPC8377 processor as the RC device. The embedded Linux application running on MPC8377 accesses FPGA with EP driver, and realizes the communication between FPGA and PowerPC processor. In the PCIe communication system of multiple embedded Power PC processors, the PCIe communication of MPC8377 is realized. One processor acts as a RC device upstream of the switch, while the other processor acts as an EP device downstream of the switch. The embedded Linux application running in RC terminal cooperates with EP driver to realize communication with EP processor. The test results of two kinds of embedded platform are given in this paper, and it is proved that they can meet the design requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP336

【参考文献】

相关期刊论文 前3条

1 贾真;林清;;PCI总线应用设计与研究[J];现代电子技术;2008年10期

2 郭绍日;张振宇;;PCI Express总线技术剖析[J];电子测试;2004年11期

3 陈世平;高分辨率卫星遥感数据传输技术发展的若干问题[J];空间电子技术;2003年03期

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本文编号：2013580