基于FPGA模拟片上多核处理器的新方法

发布时间：2018-06-13 15:22

本文选题：模拟 + 仿真　；参考：《高技术通讯》2014年07期

【摘要】：为了解决使用现场可编程门阵列(FPGA)进行大规模片上多核处理器模拟的容量限制难题,提出了一种新颖的FPGA模拟方法。该方法通过混合真实的处理器核与伪造的处理器核,使用1个或2个FPGA即可模拟整个片上多核处理器,而且可以有效克服FPGA的容量限制问题,同时又不过多损害对多核处理器行为特征的有效模拟。用此方法实现了周期精确的全芯片模拟,并使用流片后的片上多核处理器芯片对此模拟方法进行了有效性验证。实验很容易地实现了50MHz以上的模拟速度,比基于相同设计的软件仿真快10万倍以上。模拟速度的大幅度提升,使得可以启动未经修改的Linux操作系统和运行完整的多用户SPEC CPU2006 train测试集。这种混合真实处理器核与伪造处理器核的模拟方法为片上多核处理器的功能验证和性能评估提供了一种简单高效的途径。
[Abstract]:In order to solve the capacity limitation problem of large-scale on-chip multi-core processor simulation using FPGA (Field Programmable Gate Array), a novel FPGA simulation method is proposed. By mixing the real processor core with the fake processor core, one or two FPGA can be used to simulate the multi-core processor on the whole chip, and the problem of capacity limitation of FPGA can be overcome effectively. At the same time, it does not damage the effective simulation of multi-core processor behavior characteristics. This method is used to realize the full chip simulation with accurate cycle, and the validity of the simulation method is verified by using the on-chip multi-core processor chip behind the stream chip. The simulation speed of above 50MHz is easily realized, which is more than 100000 times faster than the software simulation based on the same design. The speed of the simulation is greatly improved, which makes it possible to start the unmodified Linux operating system and run the complete multiuser spec CPU2006 train test set. The simulation method of mixed real processor core and fake processor core provides a simple and efficient way to verify the function and evaluate the performance of multi-core processor on a chip.
【作者单位】：计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院计算技术研究所;中国科学院大学;龙芯中科技术有限公司;
【基金】：国家“核高基”科技重大专项课题(2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002,2012ZX01029-001-002-002) 国家自然科学基金(61221062,61100163,61133004,61173001,61232009,61222204) 863计划(2012AA010901,2012AA011002,2012AA012202,2013AA014301)资助项目
【分类号】：TP332

【相似文献】