YHFT-DX寄存器文件的设计与实现

发布时间：2018-06-15 08:01

本文选题：寄存器文件 + 全定制设计　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：YHFT-DX是采用65纳米工艺自主研发的高频、高性能32位定点超长指令字数字信号处理器，其中寄存器文件是该处理器的性能瓶颈和设计难点之一。本文根据YHFT-DX的总体结构和性能要求，确定了对该多端口寄存器文件进行全定制设计的技术路线，设计实现了一款13读9写、支持64位长型数据的32×32位寄存器文件，并对寄存器文件进行了可测性设计和低功耗设计。所设计的寄存器文件版图面积为266×302μm2，在YHFT-DX数字信号处理器芯片中得到了应用，流片后的芯片测试结果表明：典型条件下随机读写的平均功耗为8mW，，最差条件下工作频率可以达到800MHz，达到了设计目标。本文的主要贡献和创新点集中体现在以下几个方面： 1.对YHFT-DX寄存器文件进行了功能设计、时序设计以及结构设计，确定了定向通路机制，避免了写后读数据相关。根据长型数据访问特点，采用端口复用、分体布局技术在寄存器内部把端口数目从13读9写减少为10读6写，将存储阵列中端口数目和译码器数目减少了6个，使版图面积减少了22%。 2.采用全扫描设计方法来增加寄存器文件的可测试性，从而实现寄存器文件可观察性、可控制性等可测试性设计目标，并从以下方面体现其可测性：从任一写端口向任一寄存器写入数据可观察；从任一读端口向任一寄存器文件读数据，或者任一读端口通过定向通路向任一写端口读数据可观察；输入端口的控制信号实现对写地址、写使能、写数据和读数据的输入和输出工作状态可控制。 3.采用逻辑优化、操作数隔离、门控时钟、混合阈值、多级译码、电路转换等多种低功耗设计技术，降低了动态功耗和漏流功耗。典型条件下随机读写平均功耗为8mW。 4.采用结构化版图设计减少了版图面积。同时加入可测试设计后，通过改变电路结构并运用结构化版图设计方法，使得寄存器文件版图面积比传统版图设计方法减少了15%。通过更优的电路结构，提高了寄存器的性能，在译码、存储和定向通路中使用了低阈值技术降低了延时，频率在最差条件下可以达到800MHz。
[Abstract]:YHFT-DX is a high frequency, high performance 32 bit fixed point ultra long instruction word digital signal processor developed by 65 nm process. Register file is one of the performance bottlenecks and design difficulties of the processor. According to the overall structure and performance requirements of YHFT-DX, the technical route of fully customizing the multi-port register file is determined in this paper. A 32 脳 32 bit register file with 13 read and 9 writes and supporting 64 bit long data is designed and implemented. The register file is designed for testability and low power consumption. The designed register file has a layout area of 266 脳 302 渭 m ~ 2, which has been applied in YHFT-DX digital signal processor chip. The chip test results after streaming show that the average power consumption of random reading and writing is 8 MW under typical conditions, and the working frequency can reach 800 MHz under the worst condition, which achieves the design goal. The main contributions and innovations of this paper are embodied in the following aspects: 1. The function design, timing design and structure design of the YHFT-DX register file are carried out, and the directional path mechanism is determined to avoid the post-write data correlation. According to the characteristics of long data access, port multiplexing is adopted. The split layout technique reduces the number of ports from 13 read 9 write to 10 read 6 write in the register, and reduces the number of ports and decoders in the memory array by 6. Reduce the layout area by 22.2. The full scan design method is used to increase the testability of register files, so as to realize the testability design goals of register files, such as observability, controllability, etc. The testability can be observed by writing data from any write port to any register, reading data from any read port to any register file, or reading data from any read port to any write port through a directional path. Input port control signal to write address, write enable, write data and read data input and output working state can be controlled. 3. Low power design techniques such as logic optimization, Operand isolation, gated clock, hybrid threshold, multistage decoding and circuit conversion are used to reduce dynamic power consumption and leakage power consumption. Under typical conditions, the average power consumption of random reading and writing is 8 MW. 4. Structural layout design reduces layout area. After adding testability design, by changing the circuit structure and using the structural layout design method, the register file layout area is reduced by 15% compared with the traditional layout design method. The performance of the register is improved by better circuit structure, and the delay is reduced by using low threshold technique in decoding, storage and orientation paths, and the frequency can reach 800MHz under the worst conditions.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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