嵌入式存储器可测性设计及片上修复技术研究

发布时间：2018-06-16 12:05

本文选题：嵌入式存储器 + 可测性设计　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：随着半导体集成技术的发展及SoC的广泛应用，芯片结构中嵌入式存储器所占比重不断加大。而存储器本身的高密度结构和复杂的制造工艺增大了其出现物理缺陷的可能性，使其成为制约芯片成品率的关键因素。因而，研究高效的嵌入式存储器可测性设计方法以及失效存储器的修复技术变得十分重要，并具有广阔的应用前景。论文阐述了嵌入式存储器测试与修复技术的国内外研究状况，针对传统的测试和修复技术效率较低的问题，，通过分析芯片的可测性设计原理，设计了基于March16N测试算法的16k×16位SRAM内建自测试电路及其在芯片中的顶层连接电路；采用冗余寄存器代替存储器故障单元的方法，设计了基于E-fuse可编程熔丝结构的存储器片上修复系统。使用Modelsim工具对内建自测试电路进行了模拟仿真，验证了该电路功能的正确性。对修复电路进行了模拟仿真和后端设计，结果表明该系统可实现存储器故障修复，且增加的电路面积小于原存储器面积的10%，达到了预期功能。在以上研究基础上，针对芯片中需要修复的存储器较多的情况，对片上修复系统进行了优化，进一步减小修复电路占用的面积。为嵌入式存储器测试及修复技术的发展提供了技术支撑。
[Abstract]:With the development of semiconductor integration technology and the wide application of SoC, the proportion of embedded memory in chip structure is increasing. The high density structure of the memory and the complex manufacturing process increase the possibility of physical defects and make it the key factor to restrict the yield of the chip. Therefore, it is very important to study the efficient design method of the testability of embedded memory and the repair technology of the invalid memory, and it has a broad application prospect. This paper describes the research status of embedded memory test and repair technology at home and abroad. Aiming at the low efficiency of traditional test and repair technology, this paper analyzes the design principle of chip testability. A 16 k 脳 16 bit SRAM built-in self-test circuit based on March16N test algorithm and its top-level connection circuit in the chip are designed, and the method of using redundant registers instead of memory fault cells is designed. A memory on-chip repair system based on E-fuse programmable fuse structure is designed. Simulation of built-in self-test circuit with Modelsim is carried out, and the correctness of the circuit is verified. The simulation and back-end design of the repair circuit are carried out. The results show that the system can realize the memory fault repair, and the increased circuit area is less than 10% of the original memory area, which achieves the expected function. On the basis of the above research, the on-chip repair system is optimized to reduce the area occupied by the repair circuit in view of the more memory needed to be repaired in the chip. It provides technical support for the development of embedded memory test and repair technology.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333;TN47

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