一种1GHz多端口低功耗寄存器堆设计

发布时间：2018-06-20 14:47

本文选题：寄存器堆 + 单端结构　；参考：《计算机工程与科学》2015年12期

【摘要】：超标量处理器中的寄存器堆通常采用多端口结构以支持宽发射,这种结构对寄存器堆的速度、功耗和面积提出了很大的挑战。设计了一个64*64bit多端口寄存器堆,该寄存器堆能够在同一个时钟周期内完成8次读操作和4次写操作,通过对传统单端读写结构的存储单元进行改进,提出了电源门控与位线悬空技术相结合的单端读写结构的存储单元,12个读写端口全部采用传输门以加快访问速度。采用PTM 90nm、65nm、45nm和32nm仿真模型,在Hspice上进行仿真,与传统单端读写结构相比较,所提出的方法能够显著提升寄存器堆的性能,其中写1操作延时降低超过32%,总功耗降低超过45%,而且存储单元的稳定性也得到明显改善。
[Abstract]:Register file in superscalar processors usually uses multi-port structure to support wide transmission. This structure poses a great challenge to the speed, power consumption and area of register file. A 64*64bit multiport register file is designed, which can complete 8 read operations and 4 write operations in the same clock cycle. A single end read-write memory unit combining power gating and bit line suspension is proposed. All 12 read and write ports use transmission gates to speed up access. Using PTM90nmO65nm and 32nm simulation model, the simulation is carried out on HSPICE. Compared with the traditional single-ended read-write structure, the proposed method can significantly improve the performance of the register file. The write 1 operation delay is reduced by more than 32, the total power consumption is reduced by more than 45%, and the stability of the memory cell is obviously improved.
【作者单位】：上海大学微电子研究与开发中心;上海大学新型显示技术及应用集成教育部重点实验室;上海大学机电工程与自动化学院自动化系;
【分类号】：TP332.11

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