猜测并行多核体系结构模拟环境研究与实现

发布时间：2018-06-21 05:56

  本文选题：多核/众核 + 线程级猜测执行　； 参考：《国防科学技术大学》2013年硕士论文

【摘要】：多核(Multi-core)/众核(Many-core)体系结构已成为当前高性能通用处理器设计时的首选。随着工艺技术的进步,处理器芯片中集成的计算资源和存储资源越来越多,这使得以猜测的方式挖掘应用中的粗粒度并行成为可能。不少研究工作已经表明,猜测并行(Speculative Parallelization)机制能够在简化并行编程模型的同时,有效提高应用程序的性能。软件模拟一直是处理器体系结构研究的主要手段,在当前多核/众核处理器体系结构的研究中也发挥着重要作用。特别是在时间和成本受限的情况下,很多研究工作都基于软件模拟工具进行。然而,模拟速度慢一直是软件模拟工具的一个重要不足。为了支持猜测并行研究,本文着重研究了如何设计并实现一个高效的支持线程级猜测并行的多核体系结构软件模拟环境,主要研究工作与成果如下:1.TLS模拟库TLS-SL的设计与实现在深入分析现有线程级猜测执行(Thread Level Speculation,TLS)机制和相关多核/众核体系结构设计的基础上,定义了一个线程级猜测并行模拟库(TLS Simulation Library,TLS-SL),我们在开源的SESC软件模拟器上进行了实现和正确性测试。2.执行后时序分析方法(Post-Execution Timing Analysis,PETA)为解决软件模拟效率低的问题,本文还探索了SESC模拟器的加速方法,提出并实现了一种执行后时序分析方法,有效提高了模拟速度。基于这种方法,实现了PETA-sim并行模拟器,在Intel多核平台上面向Parsec基准程序的测试结果证明了这种方法的正确和有效。我们的工作为进行多核/众核平台下线程级猜测执行机制的研究奠定了很好的基础。
[Abstract]:Multi-Core Multi-Core / Multi-Core Many-Core (Many-Core) architecture has become the first choice in the design of high performance universal processors. With the development of process technology, more and more computing and storage resources are integrated into processor chips, which makes it possible to mine coarse-grained parallelism in applications by guessing. Many researches have shown that the speculative parallelization mechanism can effectively improve the performance of applications while simplifying the parallel programming model. Software simulation is the main method of processor architecture research, and it also plays an important role in the research of multi-core / multi-core processor architecture. Especially in the case of time and cost constraints, many research work is based on software simulation tools. However, the slow speed of simulation has always been an important deficiency of software simulation tools. In order to support the research of conjecture parallelism, this paper focuses on how to design and implement an efficient multi-core architecture software simulation environment that supports thread level conjecture parallelism. The main research work and results are as follows: 1. The design and implementation of TLS-SL, a TLS simulation library, is based on the in-depth analysis of the existing Thread level SpeculationTLSs mechanism and the related multi-core / crowdcore architecture design. A thread level conjecture parallel simulation library, TLS Simulation Library, TLS-SLN, is defined. We have carried out implementation and correctness testing on the open source SESC software simulator. Post-execution timing Analysis (PETAA). In order to solve the problem of low efficiency of software simulation, this paper also explores the acceleration method of SESC simulator, and proposes and implements a post-execution timing analysis method, which effectively improves the simulation speed. Based on this method, PETA-sim parallel simulator is implemented. The test results for Parsec benchmark program on Intel multi-core platform show that this method is correct and effective. Our work lays a good foundation for the research of the execution mechanism of thread level guesses in multi-core / multi-kernel platform.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
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本文编号：2047501