FT-XDSP高性能64位定点SIMD乘加部件的设计与实现

发布时间：2018-06-21 15:58

本文选题：SIMD + 乘法器　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：FT-XDSP是国防科技大学自主研发的一款超长指令字结构的64位高性能通用DSP,设计主频1.5GHz,适用于高性能计算、无线通信、视频和图像处理等方面。本文依托FT-XDSP的开发与研制,旨在研究和设计面向DSP的64位高性能定点SIMD乘加部件,以满足数字信号处理器对乘加混合运算和并行运算的处理能力。本文主要的工作和贡献如下： 1.设计和改进了64位SIMD定点乘法器,该乘法器能够实现一个有符号和无符号64位定点乘法,或者两个SIMD有符号或无符号32位定点乘法。该乘法器结构采用了提前预测的思想,对符号位进行预处理来实现SIMD功能。经过改进后,64位乘法器能够同时适用于双精度浮点53位尾数的乘法运算,而基本不影响浮点乘法的性能。改进后的乘法器在45nm工艺下的最长路径为724ps。 2.设计并实现了四站流水的64位高性能定点乘加部件。该部件集成了加减法、乘法、乘加、乘减、点积、复数乘法和MOV等各种运算,并支持32位SIMD并行处理。本文设计了定点乘加部件的体系结构和流水线,对定点乘加部件的各个流水站和关键模块进行了详细设计,包括各个流水站实现的功能和定点/浮点乘法器复用。并采用并行前缀加法器设计了定点乘加部件的单周期指令模块。 3.对定点乘加部件进行了优化、综合与验证。对定点乘加部件的关键路径进行优化,基于45nm工艺在Typical工作条件下对定点乘加部件进行了RC综合,结果表明工作频率可达1.5GHz,关键路径450ps,Cell面积89727um2,功耗17.1mW。采用功能模拟验证方法对定点乘加部件进行了详细的模块级验证和DSP内核环境下的验证,并提出了系统级验证方案。经过验证定点乘加部件功能正确。综合和验证结果表明本文的设计满足了FT-XDSP对定点乘加部件的性能和功能设计要求。
[Abstract]:FT-X DSP is a 64 bit high performance universal DSPs with super long instruction word structure developed by the University of National Defense Science and Technology. The main frequency is 1.5GHz, which is suitable for high performance computing, wireless communication, video and image processing and so on. Based on the development and development of FT-X DSP, this paper aims to study and design 64-bit fixed-point SIMD multiplicative and additive components for DSP, so as to meet the digital signal processor's ability to deal with mixed multiplication and parallel operation. The main work and contributions of this paper are as follows: 1. A 64 bit SIMD fixed-point multiplier is designed and improved. The multiplier can implement a signed and unsigned 64-bit fixed-point multiplication, or two SIMD signed or unsigned 32-bit fixed-point multiplication. The multiplier structure adopts the idea of prediction ahead of time and preprocesses the symbol bit to realize the SIMD function. The improved 64-bit multiplier can be applied to double precision floating-point 53-bit Mantissa multiplication at the same time without affecting the performance of floating-point multiplication. The longest path of the improved multiplier in 45nm process is 724 ps.2. The 64-bit high-performance fixed-point multiplication and addition component of four-station pipeline is designed and implemented. It integrates addition and subtraction, multiplication and subtraction, dot product, complex multiplication and MOV, and supports 32-bit SIMD parallel processing. In this paper, the architecture and pipeline of fixed-point multiplication and add-ons are designed, and the pipeline stations and key modules of fixed-point multiplication are designed in detail, including the functions of each pipeline station and the multiplexing of fixed-point / floating-point multipliers. The single cycle instruction module of fixed-point multiplication and adders is designed by using parallel prefix adder. The optimization, synthesis and verification of the fixed-point multiplying and adding parts are carried out. The critical path of fixed-point multiplication and addition parts is optimized. The RC synthesis of fixed-point multiplicative parts is carried out under typical operating conditions based on 45nm process. The results show that the working frequency can reach 1.5 GHz, the critical path 450 ps-cell area 89727um2, and the power consumption 17.1 MW. The modular verification of fixed-point multiplication and the verification of DSP kernel environment are carried out by using functional simulation verification method, and a system-level verification scheme is proposed. It is verified that the function of fixed point multiplying and adding parts is correct. The results of synthesis and verification show that the design of this paper meets the performance and function design requirements of FT-X DSP for fixed-point multiplication and addition components.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332.2

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