DSP64X中可配置主机并行接口的设计与验证

发布时间：2018-06-21 19:05

本文选题：DSP64X + HPI　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：DSP64X是我校自主研制的一款高性能定点数字信号处理器。它在语音、图形图像、信号处理、通信等众多领域有着广阔的应用前景。可配置主机并行接口（Host-PortInterface，简称HPI）是DSP与外部系统进行通信的一个重要并行接口部件。通过HPI，可以完成外部主设备系统与DSP内部存储空间的数据交换、DSP芯片的自举以及调试。在主从双机DSP应用系统中，通过配置HPI接口，还可以直接进行双机通信。本论文的主要研究内容和主要研究成果： ◆在研究各种可配置并行接口部件技术的基础上，根据DSP64X的总体结构和性能需求，完成了该款DSP中可配置主机并行接口部件的总体结构设计和协议设计。 ◆基于DSP64X，设计实现了一款可配置的主机并行接口，实现了与DSP64X的EDMA、外设总线控制器、中断控制器以及系统控制器的接口协议。HPI部件包含5个功能模块，分别为：外部主机接口模块、外设总线接口模块、读缓存控制模块、写缓存控制模块和EDMA接口模块。 ◆深入研究了部件内部读、写缓存的结构设计，，实现了乒乓结构的多缓存异步对接技术，从而实现外部主机与DSP之间进行并行、高速数据交换。 ◆基于当前微处理器的主要验证策略和方法，以及HPI功能结构特点的要求，完成本设计的模块级、部件级和系统级的模拟验证，为主机接口开发了完备的测试功能代码，并完成了不同层次的功能验证和时序验证，保证了可配置主机并行接口在功能上满足设计需求和时序约束要求。 ◆协助完成了基于C7YC68013芯片的仿真测试平台的设计，并在该平台上完成了对于DSP64X芯片HPI部件的所有功能验证和测试。经实际投片芯片测试，所设计的HPI部件功能正确，外部工作频率可达200MHz，可支持16位、32位数据的并行传输，最高数据带宽可达800MB。完全达到了芯片总体设计的要求。
[Abstract]:DSP 64X is a high-performance fixed-point digital signal processor developed by our university. It has a broad application prospect in many fields, such as voice, graphics and image, signal processing, communication and so on. Configurable Host parallel Interface (HPI) is an important parallel interface component for DSP to communicate with external systems. Through HPI, the self-booting and debugging of DSP chip of data exchange between the external main equipment system and the internal storage space of DSP can be completed. In the Master-Slave dual DSP application system, by configuring the HPI interface, the communication between two computers can be carried out directly. The main research contents and results of this thesis are as follows: based on the research of various configurable parallel interface components, according to the overall structure and performance requirements of DSP64X, The overall structure design and protocol design of the configurable host parallel interface in the DSP are completed. Based on DSP64X, a configurable host parallel interface is designed and implemented, and the EDMA-peripheral bus controller with DSP64X is realized. The interface protocol of interrupt controller and system controller .HPI consists of five functional modules: external host interface module, peripheral bus interface module, read buffer control module. Write buffer control module and EDMA interface module. In this paper, the structure design of internal read and write cache is deeply studied, and the asynchronous docking technology of ping-pong multi-cache is realized, so that the parallel between external host and DSP is realized. High speed data exchange. Based on the main verification strategies and methods of current microprocessor and the requirements of HPI function structure, the simulation verification of module level, component level and system level of this design is completed. Developed complete test function code for host interface, and completed different levels of function verification and timing verification. It ensures that the parallel interface of the configurable host meets the requirements of design and timing constraints in function, and accomplishes the design of simulation and test platform based on C7YC68013 chip. All functions of DSP 64X HPI are verified and tested on the platform. The test results show that the designed HPI module has the correct function, the external working frequency can reach 200 MHz, and it can support the parallel transmission of 16-bit and 32-bit data, and the maximum data bandwidth can reach 800 MB. It completely meets the requirements of the overall design of the chip.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7

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