DSP中指令Cache的研究与设计

发布时间：2018-06-26 03:27

本文选题：DSP + 指令Cache　；参考：《江南大学》2012年硕士论文

【摘要】：高速缓冲存储器(Cache)有效弥补了处理器与主存储器之间的速度差距,加快了处理器对存储器的读写速度,提高了DSP(Digital Signal Processor)系统性能。但是Cache因其面积大、速度快、访问频繁,被视为处理器芯片功耗的主要来源。如何设计一个高性能低功耗的Cache,对于DSP处理器整体性能有着重要的意义,已经成为了一个热点问题。本文设计了一种指令Cache:通过添加一个具有重装功能的Line Buffer,有效减少了CPU对Cache的访问次数,从而降低了指令Cache的相关功耗。并且在Cache发生缺失时,重装控制单元能在6个时钟周期内将片外存储单元中的指令送到CPU取指单元,有效提高了指令Cache的性能。对于指令Cache的设计主要包括基本参数的设计,指令Cache体系结构的设计,各个功能模块的设计,以及Line Buffer的设计。其中,在对指令Cache设计时,需要根据DSP处理器的具体特征合理规划好工作流程,减少指令Cache命中时间。整个指令Cache的设计采用自顶向下的设计流程,以硬件描述语言VHDL作为输入工具进行指令Cache的设计。使用Mentor公司的Modelsim对设计进行功能仿真,以SYNOPSYS公司的综合工具Design Compiler对指令Cache部分进行逻辑综合。综合和仿真结果表明:整个指令Cache的设计实现了所有预期功能,满足了路径延时的要求,在最坏情况下最长路径延时为1.66ns。通过运行3种基准测试程序得出:Line Buffer可以使CPU对指令Cache访问频率减少35%,有效降低了指令Cache的功耗。目前该设计已成功应用于32位的高端DSP中,并使其整体功耗位于0.5mW/MIPS以内。
[Abstract]:Cache can effectively bridge the speed gap between the processor and the main memory, accelerate the speed of the processor to read and write the memory, and improve the performance of the DSP (Digital signal processor) system. However, cache is regarded as the main source of power consumption because of its large area, high speed and frequent access. How to design a high performance and low power Cacheis of great significance for the overall performance of DSP processors has become a hot issue. This paper designs an instruction Cache. by adding a reload line buffer, the number of CPU access to Cache is reduced effectively, and the related power consumption of instruction cache is reduced. When cache is missing, the reload control unit can send the instructions from the off-chip memory unit to the CPU in six clock cycles, which improves the performance of the instruction cache effectively. The design of instruction cache mainly includes the design of basic parameters, the architecture of instruction cache, the design of each function module, and the design of Line buffer. In the design of instruction cache, it is necessary to reasonably plan the workflow according to the specific characteristics of DSP processor and reduce the hit time of instruction cache. The whole instruction cache design adopts the top-down design flow, and uses the hardware description language VHDL as the input tool to design the instruction cache. The function of the design is simulated by Modelsim of Mentor Company, and the instruction Cache part is logically synthesized by Design Compiler, a Synthetical tool of SYNOPSYS. The results of synthesis and simulation show that the design of the instruction cache achieves all the expected functions and meets the requirement of path delay. In the worst case, the longest path delay is 1.66 ns. By running three kinds of benchmark programs, it is concluded that: line buffer can reduce the frequency of CPU access to instruction Cache by 35 times, and effectively reduce the power consumption of instruction cache. At present, the design has been successfully applied to 32 bit high end DSP, and the overall power consumption is within 0.5 MW / MIPS.
【学位授予单位】：江南大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP368.1

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