余数系统中模加和模乘单元的设计

发布时间：2018-06-26 07:28

本文选题：余数系统 + 模2~n-2~k±1加法器　；参考：《电子科技大学》2013年硕士论文

【摘要】：过去的十几年，超大规模集成电路的集成度的提高主要是依赖于工艺特征尺寸的减小，但如今的半导体工艺已经到了极限的水平，而且又随着用户对电子产业的要求越来越高，因此集成电路亟需解决其处理速度、面积和功耗之间如何权衡的问题。余数系统具有并行处理的性质，它可以将原本单一的、复杂的处理单元划分成多个独立的、简单的处理通道，将这种方式应用在集成电路设计中，可以在不增大面积开销的基础上来提高集成电路的运行速度。对于余数系统，它的基本运算单元是模加和模乘，因此模加和模乘的算法是影响基于余数系统的集成电路性能最主要的因素。本文主要针对余数系统中的模加法器和模乘法器的设计展开了深入的研究，并且这些设计都能在一个时钟周期内完成，对今后余数系统能更好地应用在集成电路中奠定了基础。为了满足现代信号处理的复杂度，形式为2~n-2~k±1的余数基已经成为了余数系统中主要的通道，这也就意味着对这种形式的余数基的模加法器和模乘法器的研究是非常重要的。余数系统中最常用的通道包括{2~n+1,2~n,2~n-1}、{2~(2n)+1,2~n,2~(2n)-1}、{2~(n+1)+1,2~n,2~(n+1)-1}等，，而且对于类似上述这些常用的余数基通道，它们的动态范围都是2~n-2~k形式。因此对于这些余数系统，在其向二进制运算系统的转换过程中，模为2~n-2~k形式的运算单元的集成电路实现性能是决定这些余数系统的后向转换电路性能的主要因素之一，又由于后向转换对整个余数系统的集成电路性能的影响也非常大，因此一个优良性能的模2~n-2~k乘法器对整个余数系统也有非常大的意义。因此本文针对模2~n-2~k±1和2~n-2~k运算单元分别提出了其相应的算法，具体如下： (1)本文第三章主要是针对形式为2~n-2~k±1的模加法器进行了优化设计，这类模加法器是基于进位修正和并行前缀运算结构基础上提出的，它们都可以划分为四个基本的单元，分别为数据预处理、进位生成、进位修正和求和单元。其中模2~n-2~k±1加法器是根据A+B+T的最高进位对A+B+T的进位信息进行修正的，而模2~n-2~k+1加法器是根据A+B+T+2~n的最高进位对A+B+T+2~n的进位信息进行修正的。因此模2~n-2~k+1加法器与模2~n-2~k±1加法器相比，它的数据预处理单元要多一级CSA(Carry-Save Adder)压缩阵列的处理。 (2)本文在第四章提出了模2~n-2~k乘法器的算法，该乘法器巧妙地结合了两类修正方法，最终消除了求模操作。 (3)本文在第四章还提出了模2~n-2~k+1乘法器的算法，该乘法器直接对两乘数的二进制乘积结果进行多次修正，最终将其转化为一个n位的模加法运算。最后本文对所有提出的算法和与之进行对比的文献中的设计分别采用Verilog硬件描述语言进行建模，并在TSMC90纳米工艺下采用Design Compiler(DC)工具对这些Verilog模型进行逻辑综合，最后对其面积和时延报告进行分析与比较，这些比较结果可以充分说明本文提出的所有算法都具有较好的“面积x时延”特性，更适合用于集成电路的实现。
[Abstract]:In the past decade, the integration of VLSI is mainly dependent on the reduction of process feature size, but now the semiconductor technology has reached the limit level, and with the increasing demand for the electronic industry, the integrated circuit needs to solve the right between the processing speed, the area and the power consumption. The question of balance.
The remainder system has the nature of parallel processing. It can divide the original single, complex processing unit into multiple independent, simple processing channels. This method is applied to the design of integrated circuits. It can improve the running speed of the integrated circuit without increasing the area overhead. For the remainder system, its basic operation Modules are modular addition and modular multiplication, so the algorithm of modular addition and modular multiplication is the most important factor affecting the performance of integrated circuits based on residue systems.
This paper mainly focuses on the design of modulo adder and modular multiplier in the remainder system, and these designs can be completed in one clock cycle, which lays a foundation for the better application of the remainder system in the integrated circuit.
In order to meet the complexity of modern signal processing, the 2~n-2~k + 1 remainder base has become the main channel in the remainder system, which means that the research of modulo and modular multipliers for this form is very important. The most commonly used channels in the remainder system include {2~n+1,2~n, 2~n-1}, {2~ (2n) +1,2~n, 2~ (2n). ) -1}, {2~ (n+1) +1,2~n, 2~ (n+1) -1} and so on, and their dynamic range is 2~n-2~k form for these commonly used remainder based channels. Therefore, for these remainder systems, the performance of the integrated circuits that modulo the operation unit in the form of 2~n-2~k in its conversion to the binary operation system determines the remainder system One of the main factors of the performance of the back conversion circuit is also due to the great influence of backward conversion on the performance of the integrated circuit of the whole remainder system, so a good performance model 2~n-2~k multiplier also has great significance for the whole remainder system.
Therefore, the corresponding algorithm is proposed for module 2~n-2~k + 1 and 2~n-2~k operation unit respectively.
(1) the third chapter of this paper is mainly designed for the mode adder with the form of 2~n-2~k + 1. The modular adder is based on the input correction and the parallel prefix operation structure. All of them can be divided into four basic units, which are data preprocessing, the carry generation, the advance correction and the summation unit. Among them, the modulus 2~n- The 2~k + 1 adder modifies the input information of the A+B+T based on the maximum entry of the A+B+T, and the modular 2~n-2~k+1 adder modifies the input information of the A+B+T+2~n based on the maximum entry of the A+B+T+2~n. Therefore, the modular 2~n-2~k+1 adder is more CSA (Carry-Save Add) than the modulus 2~n-2~k + 1 adder. Er) the processing of the compressed array.
(2) in the fourth chapter, we propose the algorithm of modular 2~n-2~k multiplier, which cleverly combines two kinds of correction methods, and ultimately eliminates the module operation.
(3) in the fourth chapter, the algorithm of the modular 2~n-2~k+1 multiplier is also proposed. The multiplier directly corrections the result of the binary product of the two multiplier and eventually transforms it into a n bit model addition.
Finally, this paper uses Verilog hardware description language to model all the proposed algorithms and the comparison in the literature, and uses the Design Compiler (DC) tool to integrate these Verilog models under the TSMC90 nanotechnology. Finally, the area and time delay report are analyzed and compared. These comparisons are made. The results show that all the algorithms proposed in this paper have better "area X delay" characteristics and are more suitable for the realization of integrated circuits.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332.2

【参考文献】