基于超长指令字的ASIP设计与实现

发布时间：2018-06-26 12:19

本文选题：专用指令集处理器 + 超长指令字　；参考：《西安电子科技大学》2013年硕士论文

【摘要】：在数字信号处理的应用中，采用传统的通用处理器(GPP, General PurposeProcessor)或者专用集成电路(ASIC，Application Specific Integrated Circuit)难以同时兼顾灵活性和高效性方面的要求。专用指令集微处理器(ASIP, Application SpecificInstruction set Processor)结合了GPP的可编程特性和ASIC的高速性，逐渐成为在硬件实现时一个新型的研究领域。在处理器结构中，超长指令字(VLIW，Very Long Instruction Word)结构即具有支持较高的指令级并行性的能力，又能够用较为简单的控制逻辑实现，在数字信号处理领域得到了飞速的发展。本文设计了基于超长指令字的ASIP，包括硬件功能的设计和软件功能的设计：硬件方面，设计并实现了一个基于超长指令字的ASIP，并且阐述了基于超长指令字VLIW的ASIP指令集和各个处理单元的结构设计；设计了处理器的流水线结构，使用相关技术解决了流水线中的数据相关和控制相关等问题，提高了处理器的工作频率。软件方面，设计并实现了对应汇编器的，阐述了汇编器的设计方法和流程，并且在汇编器中添加了寄存器重命名和指令调度技术，，成功地提高了指令级并行性。
[Abstract]:In the application of digital signal processing (DSP), it is difficult to meet the requirements of flexibility and efficiency by using traditional GPP (General Purpose-Processor) or ASIC (ASIC Application specific Integrated Circuit). ASIP (Application specific instruction set processor), which combines the programmable characteristics of Application and the high speed of ASIC, has gradually become a new research field in hardware implementation. In the processor architecture, VLIWN very long instruction word (VLIW) architecture has the ability to support high instruction level parallelism, and can be implemented with simple control logic. It has been developed rapidly in the field of digital signal processing. This paper designs ASIP based on super-long instruction word, including hardware function design and software function design: hardware aspect, A very long instruction word based ASIP is designed and implemented, and the architecture design of ASIP instruction set and each processing unit based on VLIW is described, and the pipelined architecture of the processor is designed. The correlation technology is used to solve the problems of data correlation and control correlation in the pipeline, and the working frequency of the processor is improved. In the aspect of software, the corresponding assembler is designed and implemented. The design method and flow of assembler are described, and register renaming and instruction scheduling techniques are added to assembler, which improves the parallelism of instruction level successfully.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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