三维处理器中计算资源动态共享技术研究

发布时间：2018-07-05 06:07

本文选题：多核 + 硅通孔　；参考：《国防科学技术大学》2012年硕士论文

【摘要】：随着半导体工艺尺寸步入深亚微米和纳米级别，尺寸的缩减逐渐接近物理极限。通过提升主频来提高处理器性能的发展方向已经停滞，微处理器体系结构研究和实现转移到采用多核与众核结构提高性能的道路上。但多核与众核结构并未解决功耗墙、存储墙、片上互连延迟增加等问题，并使之进一步恶化，阻碍了微处理器性能的进一步提高。三维处理器通过采用三维集成电路技术使硅片与硅片上下直接堆叠，从而以较低成本获得更多硅片资源，进而可以集成更多缓存来解决存储墙问题。连接不同堆叠层次硅片的硅通孔具有低延迟、高通信带宽等特性，可以用来解决纳米工艺全局连线的问题。传统多处理器和多计算机上的负载不均衡问题在三维多核处理器中也存在。由于三维处理器资源众多，，部分核由于负载重导致部分资源成为性能瓶颈，而同一时刻其他核计算资源处于闲置状态的场景更加常见。针对传统二维多处理器中核间共享资源面临的共享资源粒度粗、互连延迟长、可扩展性差等问题，本文提出了一种新的资源交叉的三维处理器结构3DDRS，该结构考虑了功耗与散热平衡，同时支持计算资源动态共享。针对未来三维处理器更多层次堆叠和多种数量核心共享资源的需求，提出了3DDRS结构针对多核三维处理器的扩展原则，同时提出了计算资源共享的关键技术。由于多任务执行模式的一致性，本文在同时多线程模拟器SMTSIM的基础上扩展3DDRS的性能模拟工具3DDRS-SIM。在3DDRS-SIM中重点实现了3DDRS结构中动态共享计算资源的原理，并支持对多堆叠层次的资源共享的性能模拟。使用3DDRS-SIM对3DDRS结构面临计算密集型单任务和多任务应用的性能进行了评估。实验结果表明，基于多种计算资源共享的3DDRS结构，使三维处理器的单线程最高性能平均提升23%，整体性能平均提升12%。三维处理器结构3DDRS中多个堆叠层次计算资源的共享技术，能够动态适应负载的资源需求，提升简单众核设计下单线程应用计算的性能和处理器的整体性能，是未来三维处理器设计的良好备选。
[Abstract]:As semiconductor process size steps into deep sub-micron and nano-scale, the size reduction is gradually approaching the physical limit. The development direction of improving processor performance by raising the main frequency has been stalled. The research and implementation of microprocessor architecture has been shifted to the path of improving performance by adopting multi-core and multi-core architecture. However, the multi-core and multi-core architecture has not solved the problems of power wall, storage wall, on-chip interconnect delay and so on, which further worsen and hinder the further improvement of microprocessor performance. By using 3D integrated circuit technology to stack up and down the silicon chip directly, the 3D processor can acquire more silicon chip resources at lower cost, and then integrate more buffers to solve the storage wall problem. The silicon through holes connected to different stacked layers of silicon have the characteristics of low delay and high communication bandwidth, which can be used to solve the problem of global connection in nanotechnology. Traditional multi-processor and multi-computer load imbalance problems also exist in three-dimensional multi-core processors. Due to the large number of 3D processor resources, part of the core due to heavy load leads to part of the performance bottleneck, while other computing resources at the same time is more common in the idle state scenario. Aiming at the problems of coarse-grained shared resources, long interconnect delay, poor scalability and so on, the traditional two-dimensional multi-processor system is faced with shared resources among cores. In this paper, a new 3D processor architecture, 3DDRSs, is proposed, which takes into account the balance between power consumption and heat dissipation, and supports dynamic sharing of computing resources. In order to meet the need of multilevel stacking and multiple core sharing resources in future 3D processors, the expansion principle of 3DDRS architecture for multi-core 3D processors is proposed, and the key technology of computing resource sharing is also presented. Because of the consistency of multitask execution mode, this paper extends the 3DDRS performance simulation tool 3DDRS-SIMs based on the simultaneous multithreading simulator SMTSIM. The principle of dynamically sharing computing resources in 3DDRS architecture is implemented in 3DDRS-SIM, and the performance simulation of multi-stack level resource sharing is supported. The performance of 3D DDRS architecture facing computationally intensive single-task and multi-task applications is evaluated using 3DDRS-SIM. The experimental results show that based on the 3DDRS architecture of multi-computing resource sharing, the single thread maximum performance of 3D processor is increased by 23 per thread on average, and the overall performance is increased by an average of 12. The sharing technology of multi-layer computing resources in 3D processor architecture 3DDRS can dynamically adapt to the resource requirements of the load and improve the performance of the simple multi-core design send order thread application computing performance and the overall performance of the processor. It is a good candidate for future 3D processor design.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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