IEEE1394链路层设计及验证

发布时间：2018-07-12 18:55

本文选题：IEEE1394 + 链路层IP核　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着计算机技术的迅速发展,人们对总线的传输速度和可靠性都提出了更高的要求,IEEE1394协议作为一种高性能的串行总线技术标准,因为其具有体积小、传输速率高、可靠性高、支持异步数据和等时数据传输模式等优点,在家用电子、多媒体、网络、存储设备、航空航天等领域得到了较为广泛的应用。本文首先提出了一种与IEEE1394协议相适应的链路层IP核的设计方法,实现了1394协议中规定的关于主包、物理包和响应包三类包的发送和接收的功能。本设计中的整个IP核按照模块划分,主要包括发送TRANSMIT模块、接收RECEIVE模块、主要控制LINKSM模块、CRC校验模块、PHYINT接口模块、事物层FIFO接口模块、寄存器INT_CTRL模块等。为了提高发送和接收数据包的效率,本设计中的链路层IP核对错误包的发送和接收进行了过滤。发送时,如果数据包的包头信息出现错误,链路层会产生一个复位信号,进而消除相应错误的数据包;如果数据包的包负载信息和包头信息不一致,链路层会根据包头信息的指示对包负载进行处理,并将处理后的数据包发送到物理层。接收时,如果数据包的包头信息有错误,链路层会给产生一个错误包撤销指示信号,进而消除之前接收到的有错误的数据包;如果这个数据包的包负载信息有错误,链路层会将这个数据包存入事物层FIFO并产生一个数据包错误的指示信号。接着本文对IEEE1394链路层IP核进行了验证。为了提高验证效率,本文使用了目前验证中应用最多的通用虚拟验证方法学UVM。在综合考虑验证工作的复杂度、验证工作的必要性和模拟链路层工作环境的充分性等因素后,提出了IEEE1394链路层验证平台的搭建方法,并制订了相应的验证计划。根据验证计划的要求,编写出了300多项相关的测试向量,完成了对链路层IP核中设计的异步数据包发送、异步数据包接收、等时数据包发送、等时数据包接收和错误数据包过滤等功能的验证。根据Questasim仿真器的仿真结果可以看出,本文中所设计的链路层IP核实现了1394串行总线协议中关于链路层部分所规定的功能和链路层对错误数据包进行过滤的功能。最后完成了覆盖率的相关测试,实现了对IEEE1394链路层IP核的前期验证的评估。
[Abstract]:With the rapid development of computer technology, more demands have been put forward for the transmission speed and reliability of the bus. IEEE1394 protocol is regarded as a high performance serial bus technical standard, because of its small volume, high transmission rate and high reliability. It supports asynchronous data and isochronous data transmission mode, and has been widely used in home electronics, multimedia, network, storage devices, aerospace and other fields. In this paper, a design method of link layer IP core adapted to IEEE1394 protocol is proposed, which realizes the function of sending and receiving three kinds of packets, including main packet, physical packet and response packet, as specified in 1394 protocol. The whole IP core in this design is divided according to the module, mainly including sending TRANSMIT module, receiving RECEIVE module, controlling LINKSM module and CRC checking module, controlling PHYINT interface module, thing layer FIFO interface module, register INTCTRL module and so on. In order to improve the efficiency of sending and receiving data packets, the link layer IP check error packets are filtered in this design. When sending, if the packet header information of the packet is wrong, the link layer will produce a reset signal, which will eliminate the corresponding error packet; if the packet load information and the packet header information are inconsistent, The link layer processes the packet load according to the header information and sends the processed packet to the physical layer. When received, if there is an error in the packet header information, the link layer generates an error packet revocation indication signal, thereby eliminating the error packet previously received; if there is an error in the packet load information of the packet, The link layer stores the packet into the transaction layer FIFO and generates an indication of the packet error. Then we verify the IEEE 1394 link layer IP core. In order to improve the efficiency of verification, this paper uses the universal virtual verification methodology (UVM), which is widely used in verification. After considering the complexity of verification, the necessity of verification and the adequacy of analog link layer working environment, this paper proposes a method to build the IEEE1394 link layer verification platform, and formulates the corresponding verification plan. According to the requirements of the verification plan, more than 300 related test vectors have been written, and the asynchronous packet transmission, asynchronous data packet reception, isochronous packet transmission in the link layer IP core have been completed. Verification of isochronous packet reception and error packet filtering. According to the simulation results of the Questasim simulator, it can be seen that the link layer IP core designed in this paper realizes the functions of the link layer part of the 1394 serial bus protocol and the link layer filtering error packets. Finally, the coverage test is completed, and the previous verification of IEEE1394 link layer IP core is realized.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP336

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