基于高性能网络处理器的存储控制模块的设计与验证

发布时间：2018-07-14 09:08

【摘要】：近年来,伴随着网络规模和接口速度的增长,以通用处理器或以ASIC专用芯片为基础的传统网络设备无法在性能上达到线速处理协议的处理要求,另一方面,网络通信协议及标准快速变化更新,用户的需求不断提高,这就需要数据通信产品升级换代速度加快,开发周期缩短。网络处理器(Network Processor, NP)在这种背景下应运而生,它的出现既解决了通用处理器的低性能,又具有优于ASIC的高灵活性,能够更好的适应数据通信行业快速的发展。网络处理器作为典型的片上多处理器系统(MPSoC),对存储器的访问频率很高,因此对访存也给予了更高的要求。本文针对网络处理器芯片的应用需求,重点研究了网络处理器内部的存储控制模块,并对其实现的具体功能加以分析和验证。针对多核共享存储器造成的访存压力,存储控制模块的设计采用分层仲裁机制,将固定优先级仲裁机制与改进的轮转优先级仲裁机制相结合,既充分考虑了优先性,又保证了低优先级指令队列的公平性,更为分组读写提供了可能。接口模块作为控制单元的核心组成部分,重点研究了模块内部采用的指令缓存结构,并通过指令预取、预译码,实现指令控制信息的流水线式输出,提高了存储总线的利用率。验证的主要任务是保证设计与功能描述相符合,本文研究了目前几种主要的SoC验证技术,结合存储控制模块的功能特点,采用软件仿真与FPGA板级验证相结合的验证策略对其进行功能验证,搭建了验证平台,并且根据存储控制模块具体实现功能提出了相应的验证方案,使用Modelsim工具进行了功能仿真,并在FPGA平台上完成了板级测试,结果证实了存储控制模块能够完成多处理器对片外存储器SSRAM的访问。
[Abstract]:In recent years, with the growth of network scale and interface speed, traditional network devices based on universal processor or ASIC special chip can not meet the processing requirements of line-speed processing protocol in performance, on the other hand, Network communication protocols and standards are rapidly changing and updating, and the demand of users is increasing. Therefore, it is necessary to speed up the upgrading of data communication products and shorten the development period. Network processor (NP) emerges as the times require under this background. It not only solves the low performance of general purpose processor, but also has high flexibility than ASIC. It can better adapt to the rapid development of data communication industry. As a typical multiprocessor system (MPSoC), network processor has a high access frequency to memory. Aiming at the application requirement of network processor chip, this paper focuses on the memory control module in network processor, and analyzes and verifies its specific function. Aiming at the memory access pressure caused by multi-core shared memory, the design of storage control module adopts layered arbitration mechanism, which combines fixed priority arbitration mechanism with improved rotation priority arbitration mechanism, which fully considers priority. It also ensures the fairness of low priority instruction queue and provides the possibility of packet reading and writing. As the core part of the control unit, the interface module focuses on the instruction buffer structure used in the module, and realizes the pipelined output of the instruction control information through the instruction prefetching and decoding, and improves the utilization ratio of the storage bus. The main task of verification is to ensure that the design is consistent with the function description. In this paper, several main SoC verification techniques are studied, combined with the functional characteristics of the memory control module. Using the verification strategy of software simulation and FPGA board level verification, the verification platform is built, and the corresponding verification scheme is put forward according to the concrete function of the storage control module, and the function simulation is carried out with Modelsim tool. The results show that the memory control module can complete the multiprocessor access to the off-chip memory SSRAM.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN47

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