符合IEEE802.15.3c标准的高速低复杂度FFT处理器设计
发布时间：2018-07-25 09:42
【摘要】：近年来,支持高速短距离数据传输的无线个人局域网(WPAN)技术得到了迅速的发展。IEEE802.15.3c标准定义了60GHz频段的无线通信系统物理层(PHY),吏无线数据传输速率达到了2Gbps。从兆比特过渡到gigabit将给通信应用领域带来一次质的飞跃,可以预见60GHz无线通信技术的应用将对未来科技,经济和社会发展产生重要、重要的影响。 FFT处理器作为60GHz系统中的关键模块,其决定了整个系统的性能。本文针对60GHz无线通信系统的要求,研究了一种高数据速率、低硬件复杂度的FFT处理器,取得成果如下： 1)根据512点FFT运算的特点,选择基-25算法作为本文的实现算法。并对512点FFT运算的旋转因子分解方法进行改进,简化其每一级运算所需要的旋转因子,从而使得复数乘法的个数相对传统分解方法降低了20%： 2)分析并比较了多路延迟反馈(MDF, Multi-path delay-feedback)和多路延迟转接(MDC, Multi-path delay commutator)两种FFT处理器的硬件架构的特点,并根据60GHz系统对数据速率以及低硬件复杂度的要求,提出了一种性能与硬件消耗折衷的FFT处理器硬件实现方案。对整个FFT处理器进行了系统级仿真,采用Verilog HDL对系统进行RTL级描述并通过工具进行逻辑综合： 3)对高速FFT处理器测试方案进行了研究。搭建了基于NIOSⅡ系统与UART串口的测试平台。在Altera公司Stratix-Ⅲ FPGA芯片上对所设计的FFT处理器进行了原型验证。其数据吞吐率可达到2.65GS/s@332MHz、信号与量化噪声比(SQNR)为33.2db、消耗了7560LEs(Logical element)的硬件资源、完成512点运算需要210ns (70cycles)。符合IEEE802.15.3c协议的要求。
[Abstract]:In recent years, the wireless personal area network (WPAN) technology, which supports high-speed and short-range data transmission, has been rapidly developed. IEEE 802.15.3c standard defines the physical layer of wireless communication system in 60GHz band and the wireless data transmission rate of (PHY), officials reaches 2Gbps. The transition from megabit to gigabit will bring a qualitative leap in the field of communication applications. It can be predicted that the application of 60GHz wireless communication technology will be important to the future development of science and technology, economy and society. As a key module in 60GHz system, FFT processor determines the performance of the whole system. According to the requirements of 60GHz wireless communication system, a FFT processor with high data rate and low hardware complexity is studied in this paper. The results are as follows: 1) according to the characteristics of 512-point FFT operation, Base-25 algorithm is chosen as the implementation algorithm in this paper. The rotation factor decomposition method of 512-point FFT operation is improved to simplify the rotation factor required for each operation. Therefore, the number of complex multiplication is reduced by 20% compared with the traditional decomposition method. 2) the hardware architecture characteristics of MDF (Multi-path delay-feedback) and Multi-path delay commutator) (MDC, Multi-path delay commutator) are analyzed and compared. According to the requirements of 60GHz system for data rate and low hardware complexity, a compromise between performance and hardware consumption for FFT processor hardware implementation is proposed. The whole FFT processor is simulated at the system level. Verilog HDL is used to describe the system at RTL level and logic synthesis is carried out through tools. 3) the test scheme of high speed FFT processor is studied. A test platform based on NIOS 鈪，
本文编号：2143408
[Abstract]:In recent years, the wireless personal area network (WPAN) technology, which supports high-speed and short-range data transmission, has been rapidly developed. IEEE 802.15.3c standard defines the physical layer of wireless communication system in 60GHz band and the wireless data transmission rate of (PHY), officials reaches 2Gbps. The transition from megabit to gigabit will bring a qualitative leap in the field of communication applications. It can be predicted that the application of 60GHz wireless communication technology will be important to the future development of science and technology, economy and society. As a key module in 60GHz system, FFT processor determines the performance of the whole system. According to the requirements of 60GHz wireless communication system, a FFT processor with high data rate and low hardware complexity is studied in this paper. The results are as follows: 1) according to the characteristics of 512-point FFT operation, Base-25 algorithm is chosen as the implementation algorithm in this paper. The rotation factor decomposition method of 512-point FFT operation is improved to simplify the rotation factor required for each operation. Therefore, the number of complex multiplication is reduced by 20% compared with the traditional decomposition method. 2) the hardware architecture characteristics of MDF (Multi-path delay-feedback) and Multi-path delay commutator) (MDC, Multi-path delay commutator) are analyzed and compared. According to the requirements of 60GHz system for data rate and low hardware complexity, a compromise between performance and hardware consumption for FFT processor hardware implementation is proposed. The whole FFT processor is simulated at the system level. Verilog HDL is used to describe the system at RTL level and logic synthesis is carried out through tools. 3) the test scheme of high speed FFT processor is studied. A test platform based on NIOS 鈪，
本文编号：2143408
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