基于DMA机制的高性能X-QDSP片上AXI总线桥接控制器的设计与实现
发布时间：2018-07-26 12:34
【摘要】：随着数字信号处理器（DSP）处理能力的不断加强，总线技术从单总线到多总线的不断进步，实现数据的高速传输和多总线结构控制成了现代DSP设计的关键技术之一。X-QDSP是我校自主研发的一款高性能DSP，该芯片拥有复杂的总线系统，内部总线控制中心Switch Bus维护了8套读写总线，且与片上总线AXI完全不同。为解决具有AXI接口的SRIO IP核与系统总线之间的高速互联，本文设计了一款128位的AXI总线桥接控制器，用于实现AXI与片内不同总线协议之间的无缝对接。 基于多总线结构控制的复杂性，，本文深入分析了QDSP中部件间的传输协议，设计了固定优先级和令牌轮转结合的总线仲裁机制，保证数据传输的畅通。 为实现多样化数据传输目的，设计了4个独立并发的读写通道构成的AXI总线桥接控制器，其中2个SRIO主机通道处理DSP内核启动的数据传输，具有DMA功能的AXI总线桥接控制器SRIO主机通道完成数据传输的后台操作；2个SRIO从机通道处理SRIO部件启动的数据传输，该从机通道直接接收来自SRIO部件的传输请求，并将其转化为Switch Bus总线上的传输命令。 根据各通道传输特点，采用高速缓冲结构有效解决了数据的合并、拆分控制和地址不对齐传输等技术难点。采用状态机集中控制方式实现了不同传输协议、不同位宽的总线之间的桥接互联，保证数据传输的高效性。采用异步FIFO技术设计了深度为4的异步FIFO控制器，实现了SRIO部件与芯片系统总线的异步对接，解决了系统总线频率和SRIO工作频率不一致的问题。 论文对桥接控制器进行了充分的模块级、部件级和系统级功能模拟验证，并统计了代码覆盖率。验证结果表明，该部件功能正确，满足系统设计要求。 论文基于65nmCMOS工艺对桥接控制器进行了逻辑综合，并对设计进行了结构和时序优化。综合结果表明，在工艺最恶劣情况下，AXI总线桥接控制器工作频率可以达到500MHz，达到了预期设计目标。
[Abstract]:With the development of digital signal processor (DSP) processing ability, bus technology is developing from single bus to multi-bus. The realization of high-speed data transmission and multi-bus structure control has become one of the key technologies in modern DSP design. X-QDSP is a high-performance DSP developed by our university. The chip has a complex bus system. The internal bus control center (Switch Bus) maintains 8 sets of read and write buses, which are completely different from the on-chip bus (AXI). In order to solve the high speed interconnection between SRIO IP core with AXI interface and system bus, a 128-bit AXI bus bridge controller is designed to realize seamless docking between AXI and different bus protocols. Based on the complexity of multi-bus structure control, this paper deeply analyzes the transmission protocol between components in QDSP, designs a bus arbitration mechanism combining fixed priority and token rotation to ensure the smooth transmission of data. In order to achieve the purpose of diversified data transmission, a AXI bus bridge controller composed of four independent concurrent read and write channels is designed, in which two SRIO host channels handle data transmission initiated by the DSP kernel. The AXI bus bridging controller with DMA function, the SRIO host channel completes the background operation of data transmission, two SRIO slave channels handle the data transmission initiated by the SRIO component, and the slave channel directly receives the transmission request from the SRIO part. It is transformed into the transmission command on the Switch Bus bus. According to the transmission characteristics of each channel, the data merging, splitting control and address misalignment transmission are effectively solved by using the cache structure. The state machine centralized control method is used to realize the bridge interconnection between different transmission protocols and different bit width buses to ensure the high efficiency of data transmission. The asynchronous FIFO controller with depth of 4 is designed by using asynchronous FIFO technology. The asynchronous connection between the SRIO component and the chip system bus is realized, and the problem that the frequency of the system bus is inconsistent with the frequency of the SRIO is solved. In this paper, the bridge controller is fully simulated at module level, component level and system level, and the code coverage is calculated. The verification results show that the function of the part is correct and meets the requirements of system design. In this paper, the logic synthesis of bridge controller based on 65nmCMOS process is carried out, and the structure and timing of the design are optimized. The results show that the operating frequency of the AXI bus bridge controller can reach 500 MHz under the worst process conditions, and the expected design goal is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
本文编号：2146030
[Abstract]:With the development of digital signal processor (DSP) processing ability, bus technology is developing from single bus to multi-bus. The realization of high-speed data transmission and multi-bus structure control has become one of the key technologies in modern DSP design. X-QDSP is a high-performance DSP developed by our university. The chip has a complex bus system. The internal bus control center (Switch Bus) maintains 8 sets of read and write buses, which are completely different from the on-chip bus (AXI). In order to solve the high speed interconnection between SRIO IP core with AXI interface and system bus, a 128-bit AXI bus bridge controller is designed to realize seamless docking between AXI and different bus protocols. Based on the complexity of multi-bus structure control, this paper deeply analyzes the transmission protocol between components in QDSP, designs a bus arbitration mechanism combining fixed priority and token rotation to ensure the smooth transmission of data. In order to achieve the purpose of diversified data transmission, a AXI bus bridge controller composed of four independent concurrent read and write channels is designed, in which two SRIO host channels handle data transmission initiated by the DSP kernel. The AXI bus bridging controller with DMA function, the SRIO host channel completes the background operation of data transmission, two SRIO slave channels handle the data transmission initiated by the SRIO component, and the slave channel directly receives the transmission request from the SRIO part. It is transformed into the transmission command on the Switch Bus bus. According to the transmission characteristics of each channel, the data merging, splitting control and address misalignment transmission are effectively solved by using the cache structure. The state machine centralized control method is used to realize the bridge interconnection between different transmission protocols and different bit width buses to ensure the high efficiency of data transmission. The asynchronous FIFO controller with depth of 4 is designed by using asynchronous FIFO technology. The asynchronous connection between the SRIO component and the chip system bus is realized, and the problem that the frequency of the system bus is inconsistent with the frequency of the SRIO is solved. In this paper, the bridge controller is fully simulated at module level, component level and system level, and the code coverage is calculated. The verification results show that the function of the part is correct and meets the requirements of system design. In this paper, the logic synthesis of bridge controller based on 65nmCMOS process is carried out, and the structure and timing of the design are optimized. The results show that the operating frequency of the AXI bus bridge controller can reach 500 MHz under the worst process conditions, and the expected design goal is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
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本文编号：2146030
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