DVI接收端模拟部分电路研究与实现
发布时间：2018-07-26 15:55
【摘要】：1999年，DDWG工作小组发布了数字视频接口标准DVI1.0标准，DVI技术的出现，革新了整个视频接口技术和市场。DVI作为一种优秀的视频接口技术，一经提出，就迅速得到世界范围内业界人士和厂商的大力支持，经过十四年的发展，如今DVI接口在视频领域中的应用非常广泛。 DVI接口采用TMDS传输协议，支持从VGA到UXGA的显示标准，单条TMDS链路时钟频率为25MHz～165MHz，数据速率为250Mbps～1.65Gbps。本文基于DVI1.0标准，对TMDS数据传输模式、TMDS链路结构以及DVI接口系统结构进行分析，给出了DVI接收端数据流向的功能框图，并且针对各个模块进行功能分析，重点研究了DVI接收端模拟部分电路的实现，主要包括三个部分：高速差分接收单元、3倍过采样数据恢复电路和12相等相位差时钟输出电荷泵锁相环电路。详细介绍这些功能模块的电路实现原理，，并且在仔细研究常用电路结构性能的基础上，对电平转换电路、鉴频鉴相器、电荷泵、压控振动器等传统电路结构分别进行优化，提出创新解决方案。 本文采用SMIC0.11μm混合工艺，使用Cadence公司的Virtuoso工具实现电路设计； Spingsoft公司的Laker工具完成版图设计；整体版图面积为264x145μm2。使用Synopsys公司的Hspice软件完成对电路的前仿真和版图的后仿真。后仿真结果表明，电路性能比较理想，完全能够满足DVI1.0标准数据传输要求。VGA分辨率模式时，接收时钟频率为25MHz，数据速率为250Mbps，PLL在3.6μs内锁定，系统在5.3μs内稳定工作，时钟信号周期间抖动峰-峰值为1.36%； UXGA分辨率模式时，接收时钟频率为165MHz，数据速率为1.65Gbps，PLL在2μs内锁定，系统在4.5μs内稳定工作，时钟信号周期间抖动峰-峰值为0.59%。
[Abstract]:In 1999, the Digital Video Interface Standard (DVI1.0) was released by the working Group of DWG, which revolutionized the whole video interface technology and the market. DVI as a kind of excellent video interface technology, once it was put forward, After 14 years of development, the DVI interface is widely used in the field of video. The DVI interface uses TMDS transport protocol. It supports the display standard from VGA to UXGA. The clock frequency of single TMDS link is 25MHz / 165MHz and the data rate is 250Mbps1.65Gbps. Based on the DVI1.0 standard, this paper analyzes the link structure of TMDS data transmission mode and the structure of DVI interface system, gives the function block diagram of the data flow direction of DVI receiver, and analyzes the function of each module. This paper focuses on the realization of analog circuit in DVI receiver, which consists of three parts: high speed differential receiving unit 3 times oversampling data recovery circuit and 12 equal phase difference clock output charge pump phase-locked loop circuit. The circuit realization principle of these functional modules is introduced in detail. On the basis of careful study of the common circuit structure and performance, the traditional circuit structures, such as level conversion circuit, frequency discriminator, charge pump, voltage controlled vibrator and so on, are optimized respectively. Propose innovative solutions. In this paper, the SMIC0.11 渭 m hybrid technology is used to realize the circuit design using the Virtuoso tool of Cadence Company, and the Laker tool of Spingsoft Company to complete the layout design. The overall layout area is 264x145 渭 m2. The Hspice software of Synopsys Company is used to finish the pre-simulation and post-emulation of the circuit. The simulation results show that the circuit performance is ideal and can meet the requirements of DVI1.0 standard data transmission. The receiving clock frequency is 25 MHz, the data rate is 250 MbpsPLL locked in 3.6 渭 s, and the system works stably in 5.3 渭 s. In the UXGA resolution mode, the received clock frequency is 165MHz, the data rate is 1.65GbpsPLL is locked within 2 渭 s, the system works stably within 4.5 渭 s, and the jitter peak is 0.59mm during the clock signal cycle.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7;TN432
[Abstract]:In 1999, the Digital Video Interface Standard (DVI1.0) was released by the working Group of DWG, which revolutionized the whole video interface technology and the market. DVI as a kind of excellent video interface technology, once it was put forward, After 14 years of development, the DVI interface is widely used in the field of video. The DVI interface uses TMDS transport protocol. It supports the display standard from VGA to UXGA. The clock frequency of single TMDS link is 25MHz / 165MHz and the data rate is 250Mbps1.65Gbps. Based on the DVI1.0 standard, this paper analyzes the link structure of TMDS data transmission mode and the structure of DVI interface system, gives the function block diagram of the data flow direction of DVI receiver, and analyzes the function of each module. This paper focuses on the realization of analog circuit in DVI receiver, which consists of three parts: high speed differential receiving unit 3 times oversampling data recovery circuit and 12 equal phase difference clock output charge pump phase-locked loop circuit. The circuit realization principle of these functional modules is introduced in detail. On the basis of careful study of the common circuit structure and performance, the traditional circuit structures, such as level conversion circuit, frequency discriminator, charge pump, voltage controlled vibrator and so on, are optimized respectively. Propose innovative solutions. In this paper, the SMIC0.11 渭 m hybrid technology is used to realize the circuit design using the Virtuoso tool of Cadence Company, and the Laker tool of Spingsoft Company to complete the layout design. The overall layout area is 264x145 渭 m2. The Hspice software of Synopsys Company is used to finish the pre-simulation and post-emulation of the circuit. The simulation results show that the circuit performance is ideal and can meet the requirements of DVI1.0 standard data transmission. The receiving clock frequency is 25 MHz, the data rate is 250 MbpsPLL locked in 3.6 渭 s, and the system works stably in 5.3 渭 s. In the UXGA resolution mode, the received clock frequency is 165MHz, the data rate is 1.65GbpsPLL is locked within 2 渭 s, the system works stably within 4.5 渭 s, and the jitter peak is 0.59mm during the clock signal cycle.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7;TN432
【参考文献】
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