基于32nm高性能微处理器向量控制部件的物理设计
发布时间：2018-07-28 18:23
【摘要】：通用CPU是信息产业的基础部件，可广泛应用在国防安全、计算机、工业控制、航空航天等重要领域。开展我国自己的通用CPU研发工作的重要性是不言而喻的。 龙芯作为我国第一款自主研发的通用CPU结束了我国无芯的历史。而本文的研发背景正是基于龙芯最新研发的64位通用CPU龙芯3C的物理设计过程。本文详细记述了龙芯3C向量控制部件的物理设计全过程。设计过程主要应用了Synopsys公司的物理设计规范流程，即先通过综合软件Design Compiler对完成改写的代码进行综合优化，得到满足要求的门级网表。之后通过IC Compiler对设计进行详细的布局规划，通过解决16块四写四读寄存器堆和约束标准单元的摆放位置等问题，使模块的拥塞和时序满足要求。在此基础上展开时钟树综合以及布线等工作。 龙芯3C面向高性能计算和服务器应用，目标工作频率为1.25GHz，整体功耗15W。借助国际领先的32nm制造工艺以及标准的EDA设计流程，，本文设计模块最终成功达标。
[Abstract]:General CPU is the basic part of information industry. It can be widely used in national defense security, computer, industrial control, aerospace and other important fields. The importance of developing our own general CPU research and development work is self-evident. As the first self-developed general purpose CPU in China, Godson has ended the history of core-less in our country. The research background of this paper is based on the physical design process of 64 bit general purpose CPU Ronson 3C. In this paper, the whole process of the physical design of the Ronson 3C vector control unit is described in detail. The design process mainly applies the physical design specification flow of Synopsys Company, that is to say, through the comprehensive software Design Compiler, the rewritten code is optimized synthetically, and the gate network table that meets the requirements is obtained. After that, the detailed layout planning of the design is carried out by IC Compiler. By solving the problems of 16 blocks of four-write and four-read register file and the placement of the constraint standard unit, the congestion and timing of the module can meet the requirements. On this basis, clock tree synthesis and cabling are carried out. Ronson 3C is designed for high performance computing and server application. The target frequency is 1.25 GHz, and the overall power consumption is 15W. With the help of international leading 32nm manufacturing process and standard EDA design process, the design module of this paper is successfully up to standard.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN402;TP332
本文编号：2151209
[Abstract]:General CPU is the basic part of information industry. It can be widely used in national defense security, computer, industrial control, aerospace and other important fields. The importance of developing our own general CPU research and development work is self-evident. As the first self-developed general purpose CPU in China, Godson has ended the history of core-less in our country. The research background of this paper is based on the physical design process of 64 bit general purpose CPU Ronson 3C. In this paper, the whole process of the physical design of the Ronson 3C vector control unit is described in detail. The design process mainly applies the physical design specification flow of Synopsys Company, that is to say, through the comprehensive software Design Compiler, the rewritten code is optimized synthetically, and the gate network table that meets the requirements is obtained. After that, the detailed layout planning of the design is carried out by IC Compiler. By solving the problems of 16 blocks of four-write and four-read register file and the placement of the constraint standard unit, the congestion and timing of the module can meet the requirements. On this basis, clock tree synthesis and cabling are carried out. Ronson 3C is designed for high performance computing and server application. The target frequency is 1.25 GHz, and the overall power consumption is 15W. With the help of international leading 32nm manufacturing process and standard EDA design process, the design module of this paper is successfully up to standard.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN402;TP332
【参考文献】
相关期刊论文 前1条
1 韩威;江川;;ASIC集成电路的可测性设计与技术实现[J];计算机科学;2009年04期
相关硕士学位论文 前1条
1 栾晓琨;基于QX多核芯片的层次化物理设计[D];国防科学技术大学;2009年
本文编号：2151209
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2151209.html
