基于LLVM的专用CPU后端移植分析与设计

发布时间：2018-07-29 15:40

【摘要】：微处理器的研发不仅是硬件的设计和制作,还包括软件部分的设计。软件设计主要是编译器的移植,编译器移植是微处理器开发的基础,它可以在很大程度上缩短微处理器的研发周期。当前大部分编译器开发人员选用GCC作为目标处理器的支持,但是GCC使用的是RTL语言,由于RTL语言非常抽象复杂,后端移植的文档匮乏,这使得GCC后端移植的难度很大。此时,如何快速实现编译器后端移植就成为了微处理器研发中的一个难题。为了完成微处理器软件部分的设计并缩短微处理器的研发周期,本文选用了近几年兴起的新型编译器架构LLVM。本文的研究内容主要分为三个部分:首先,本文详细分析了LLVM的编译架构和后端移植机制。LLVM是源于2000年美国伊利诺斯大学的一个开源项目,创始人是Chris Lattner。LLVM的内容可以分为三个部分:LLVM中间表示、集成库、工具集。LLVM的开发语言是C++,它是典型的三段式结构:前端、中端、后端。LLVM清晰的层次框架和详细的说明文档使得LLVM后端移植工作变得简单易行。本文重点介绍了LLVM的后端设计。LLVM后端提供了很多可重定向目标特性的结构支持。LLVM的后端也叫代码生成器,它分为通用的代码生成器和后端移植接口。通用的代码生成器集成了所有目标处理器共有的功能,不依赖于特定的处理器。而后端移植接口为特定的目标处理器提供了移植接口,实现不同目标处理器之间的特征描述。为了支持不同的目标处理器,生成指定的后端代码生成器,只需要对不同的处理器进行特征描述,然后用通用代码生成器和后端移植接口共同去实现后端代码生成器。其次,本文重点介绍了目标处理器的体系结构和特征。目标处理器是我国自主研发的一款基于DSP的专用处理器,简称STX。STX使用了典型的VLIW结构,可以在单个时钟周期内并行执行多条指令,大大地提高了处理器的执行效率。处理器从体系结构的角度有两类:精简指令集处理器(RISC)、复杂指令集处理器(CISC)。STX采用了RISC指令集,STX有大量的寄存器(包括32个通用寄存器和6个控制寄存器)和32位指令集,它的寻址模式简单,6种不同的异常处理使得处理器的运行更加安全可靠。STX的功耗低、面积小,它有着非常清晰的层次结构和模块化的设计思想,这样使得芯片的设计更加人性化,更易于修改和完善。然后,本文给出了详细的后端移植过程以及测试结果。为了实现LLVM对处理器STX的支持,LLVM的后端移植接口是非常重要的。LLVM的后端移植接口功能主要包括全局描述实现、寄存器描述实现、指令集描述实现、汇编输出描述实现等。为使程序开发人员更加简单方便地进行目标处理器信息的描述,LLVM工具中设计了一个非常灵活方便的工具TableGen,其是用于记录目标处理器信息的描述性语言,对于STX的所有特征实现,都需要用TableGen语言和C++语言来描述。整个移植工作可以分为td文件的描述和C++文件的描述。TableGen主要用于将td文件转换成为目标处理器所对应的C++代码。通过这些移植接口对目标处理器STX进行描述,最终实现LLVM对STX的支持。
[Abstract]:The research and development of the microprocessor is not only the design and production of the hardware, but also the design of the software part. The software design is mainly the transplant of the compiler. The compiler transplantation is the foundation of the microprocessor development. It can greatly shorten the development cycle of the microprocessor. Most compiler developers choose GCC as the target processor at present. Support, but GCC uses the RTL language, because the RTL language is very abstract and complex, the back end transplant is scarce, which makes the GCC back-end transplant very difficult. At this time, how to quickly implement the compiler back end transplantation has become a difficult problem in the microprocessor research and development. The research cycle of LLVM. is divided into three parts: first, this paper analyzes the compiler architecture of LLVM and the back-end transplant mechanism.LLVM is an open source project originate from the American University of Illinois in 2000, and the founder is the inside of Chris Lattner.LLVM. The capacity can be divided into three parts: the LLVM intermediate representation, the integration library, the development language of the tool set.LLVM is C++, which is a typical three segment structure: the front, middle, back end.LLVM clear hierarchical framework and detailed description documents make the LLVM back end migration easier and easier. This article focuses on the back end of the LLVM design, which provides the.LLVM back end. Many redirecting target features support the back end of the.LLVM, also called a code generator, which is divided into a common code generator and a back end port. The common code generator integrates all the common functions of the target processor, not on a specific processor. The back end migration interface provides the specific target processor. In order to support different target processors, to generate the specified back end code generator, it only needs to describe the characteristics of different processors, and then use the universal code generator and the back end transplant interface to implement the back end code generator. Secondly, this paper focuses on this paper. The architecture and characteristics of the target processor. The target processor is a special processor based on DSP in our country. The STX.STX uses a typical VLIW structure, which can execute multiple instructions in a single clock cycle, greatly improving the execution efficiency of the processor. The processor has two types of architecture from the perspective of Architecture: fine The simple instruction set processor (RISC), the complex instruction set processor (CISC).STX uses the RISC instruction set, STX has a large number of registers (including 32 general registers and 6 control registers) and 32 bit instruction set, its addressing mode is simple, 6 different kinds of exception handling make the processor run more secure and reliable, the power consumption of.STX is low and the area is small. With a very clear hierarchy and modular design, this makes the chip more humanized, easier to modify and perfect. Then, this article gives a detailed back end migration and test results. In order to implement LLVM's support for processor STX, the back end port of the LLVM is a very important back end shift of the.LLVM. The function of the implant interface mainly includes global description implementation, register description implementation, instruction set description implementation, assembly output description and so on. In order to make program developers more simple and convenient to describe the information of the target processor, a very flexible and convenient tool, TableGen, is designed in the LLVM tool, which is used to record the target processor. Descriptive language of information, for all features of STX, needs to be described in TableGen and C++ languages. The entire migration work can be divided into TD file description and C++ file description.TableGen mainly for converting TD files into C++ code corresponding to target processors. A description is made to ultimately support LLVM's support for STX.
【学位授予单位】：成都理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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